Application Specific Integrated Circuit Design Engineer

Intelliswift - An LTTS Company; Markham; On-site; CAD 80,000 - 100,000; Full time

Job summary

Join a forward-thinking company as an Application Specific Integrated Circuit Design Engineer, where your expertise in ASIC implementation and timing analysis will be pivotal. In this mid-senior level role, you'll develop and manage timing constraints for complex designs while collaborating closely with design and physical implementation teams. Your skills in industry-standard EDA tools and scripting will help drive innovative solutions in semiconductor manufacturing. If you thrive in a dynamic environment and are passionate about pushing the boundaries of technology, this opportunity is perfect for you.

Qualifications

• 10+ years of experience in ASIC implementation and CAD methodology.
• Expertise in ASIC EDA tools and scripting languages.

Responsibilities

• Develop timing constraints and signoff for multi-corner designs.
• Engage with design teams to address timing requirements.

Skills

ASIC Implementation

Timing Analysis

STA Constraints Generation

Problem Solving

Communication Skills

Multi-tasking

Tools

Synopsys DC

Primetime

TCL

Perl

Python

Job description

Application Specific Integrated Circuit Design Engineer

Direct message the job poster from Intelliswift - An LTTS Company

KEY RESPONSIBILITIES:

1. Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs.
2. Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management.
3. Engaging closely with block and SoC design teams to understand the design requirements, STA constraints, and convergence challenges.
4. Engaging closely with physical implementation teams to ensure designs meet QoR and debug timing failures.

PREFERRED EXPERIENCE:

1. 10+ years of professional experience in ASIC implementation and CAD methodology, preferably experience closing timing of high performance designs.
2. Demonstrated ability in areas of ASIC STA constraints generation, timing analysis, timing convergence, and ECOs, at both block and full chip level.
3. Implementation experience and knowledge handling multi-voltage design is expected. STA closure of low power and multi-power mode designs is an added advantage.
4. Expertise in industry standard ASIC EDA tools, including Synopsys DC and Primetime is required.
5. Proficiency in scripting language, such as, TCL, Perl and/or Python.
6. Experience developing scripts to automate design flow, analysis.
7. Hands-on experience with Physical Design implementation is a plus.
8. Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams.
9. Strong analytical/problem solving skills and pronounced attention to details.

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Information Technology

Industries

Semiconductor Manufacturing