Analog Layout Engineer

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

In this role, you will...

1. Carry out layout feasibility studies on various circuit designs in collaboration with senior analog designers. The goal will be to find the best possible solution considering various trade-offs and discussions with team members.
2. Create layouts of assigned analog blocks by adhering to the steps of floor planning, placement and routing.
3. Conduct thorough verification checks such as DRC, ANT, LVS, PERC, EM, IR to ensure the final layout possesses the highest level of quality.
4. Investigate new features within the layout tools and processes used for creating layouts with the aim of enhancing productivity.
5. Provide regular status updates, participate in team meetings and share experiences with the rest of the group.

The Must Haves:

1. Bachelor's degree in Electrical Engineering or related field, with 1-5 years of relevant industry experience.
2. Experience in custom analog and mixed signal layout design with a strong knowledge of deep sub-micron CMOS devices (e.g. Finfet transistors).
3. Highly motivated with strong team player skills, exhibits a positive can-do attitude and ability to seamlessly integrate into an existing team culture.
4. Strong communication and interpersonal skills to collaborate with cross-functional teams.
5. Experience in custom layout design of Analog/Mixed Signal designs (e.g. ADC, DAC, PLL, SERDES …)
6. Proficiency in using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre, Ansys Totem …) and familiarity with layout design flows for advanced technology nodes.
7. Strong analytical and problem-solving skills to identify and address layout-related issues efficiently.
8. Proficient in layout techniques for Floor Planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing.
9. Meticulous attention to details, ensuring the highest level of accuracy and quality in all layout designs.
10. Familiarity with semiconductor manufacturing processes and foundry technologies.
11. Ability to thrive in a fast-paced, dynamic work environment and adapt quickly to changing project requirements.
12. Solid understanding of RC delay, electromigration, and coupling effects.
13. Familiarity with guard rings, DNW, PN junctions, advanced process effects such as LOD, OSE, WPE.
14. High level of proficiency in interpreting DRC, PERC, ANT, ERC and LVS.
15. Ability to identify failure-prone circuit and layout structures and proactively work with circuit designers to resolve problems.

The Assets:

1. Scripting skills in PERL or SKILL are a plus, but not required.

Pay Range:

The annual pay range for this position is $83,900 - $134,100.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.