AMS Mixed Signal Co-Sim Verification Engineering, Sr Engineer

Synopsys, Inc.; Markham; On-site; CAD 80,000 - 120,000; Full time

Job summary

An innovative company seeks a motivated Mixed Signal AMS Co-Simulation Verification Engineer to join their dynamic design team. This role involves collaborating with experts in digital, analog, and mixed-signal engineering to verify cutting-edge SERDES products for Backplane Ethernet, PCIe, SATA, and USB technologies. The successful candidate will engage in setting up complex testbenches, analyzing functionalities, and ensuring the reliability of high-speed data recovery circuits. If you are passionate about pushing technological boundaries and thrive in a collaborative environment, this opportunity is for you.

Qualifications

• Strong theoretical and practical background in high-speed data recovery circuits.
• Experience in analog circuitry including bandgap references and opamps.

Responsibilities

• Setting up UVM and VMM SystemVerilog testbenches for mixed-signal designs.
• Analyzing and verifying functionalities of SERDES.

Skills

Perl

Python

Unix shell

Verilog

SystemVerilog

Analog circuitry

Job description

Seeking a Mixed Signal AMS Co-Simulation Verification Engineer

We are looking for a motivated and innovative mixed signal AMS co-simulation verification engineer with a strong theoretical and practical background in high-speed data recovery circuits. Working as part of an experienced mixed-signal design team, the candidate will be involved in verifying current and next-generation Backplane Ethernet, PCIe, SATA, and USB 2/3/4 SERDES products. This position offers an excellent opportunity to collaborate with a team of digital, analog, and mixed signal engineers responsible for delivering high-end mixed-signal designs.

Responsibilities include:

• Setting up UVM and VMM SystemVerilog testbenches to co-simulate mixed-signal designs in environments where analog and digital coexist
• Analyzing and verifying the functionalities of SERDES
• Defining and tracking verification test plans
• Debugging simulation failures in both analog and digital domains
• Creating top-level analog testbenches for SERDES
• Performing physical layout reliability analysis for SERDES

Requirements:

• Proficiency in scripting languages such as Perl, Python, and Unix shell
• Familiarity with Verilog and SystemVerilog
• Experience or knowledge of analog circuitry, including bandgap references, opamps, PLLs, and Transmitter/Receiver designs

Our Silicon IP business focuses on integrating more capabilities into SoCs quickly. We offer the world's broadest portfolio of silicon IP—pre-designed blocks of logic, memory, interfaces, analog, security, and embedded processors—helping customers meet performance, power, and size requirements while reducing time to market and risk.

At Synopsys, we are at the forefront of innovations transforming work and play, including self-driving cars, artificial intelligence, cloud computing, 5G, and the Internet of Things. These breakthroughs are shaping the Era of Smart Everything, powered by our advanced chip design and software security technologies. If you share our passion for innovation, we look forward to meeting you.