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ICsense is seeking a Senior Digital Design Engineer to study, design and verify high-quality ICs. You will lead the digital content of mixed-signal ASICs and coordinate with customers, suppliers, and internal teams on a global scale.
The role requires hands-on front-end design in VHDL/Verilog/SystemVerilog, plus verification with SystemVerilog/UVM and strong collaboration skills. English fluency and a proactive mindset are essential.
The job location can be Leuven or Ghent.
Scope
The Senior Digital Design Engineer is responsible for the study, design and verification of high quality ICs, technical team lead in challenging projects and the coaching of junior engineers.
Responsibilities
Competencies
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