Image Sensor Digital Design and Verification Engineer

eyeo; Antwerpen; Sur place; EUR 90 000 - 130 000; Plein temps

Résumé du poste

eyeo seeks an Image Sensor Digital Design and Verification Engineer to design and verify complex digital circuits within sensor architecture. You will define module architectures, implement RTL, and drive verification strategies at block and top levels, enabling robust, high-performance CMOS image sensor devices.

The role collaborates across mixed-signal, analog, and system teams in a fast-paced startup environment, contributing to advanced image sensor technology and on-chip processing

Qualifications

• Master’s or PhD in Electrical Engineering, Microelectronics, or Physics or related field.

Responsabilités

• Define and implement digital blocks for CMOS image sensor products.

Connaissances

Digital IC design

Verilog

SystemVerilog

RTL design

Verification

Python scripting

Linux environment

Git

Cadence Xcelium/IES

DFT & BIST

VHDL

C/C++/Scripting

Formation

Master’s or PhD in Electrical Engineering, Microelectronics, or Physics or related field

Outils

Cadence Xcelium/IES

Mentor Questa

Git / SVN

Description du poste

Job Title

Image Sensor Digital Design and Verification Engineer

Location

Antwerp, Belgium

Reports To

Design Center Manager

About eyeo

eyeo is an innovative, fast-growing start-up that brings groundbreaking technology in the image sensor space. Our advanced color splitter technology has the potential to disrupt a $25 billion market in the coming years, enabling transformative advancements across industries such as consumer electronics, automotive, medical imaging, and surveillance. You will have the unique opportunity to shape the future of our product offerings and contribute directly to our mission of revolutionizing the imaging technology sector. If you're passionate about driving innovation and want to build the future of imaging, we want you on our team!

About the Role

As Image Sensor Digital Design and Verification Engineer, you will be responsible for designing and verifying complex digital circuits integrated into the sensor’s digital architecture, ensuring robust functionality, performance, and quality throughout the development cycle.

You will define the module architecture and interfaces and design the RTL accordingly.

You will develop and execute verification strategies at both block and top level, including constrained-random and directed test environments. The role involves defining verification plans, coverage metrics, and closure targets, as well as building reusable verification components and infrastructure. You will run simulations and regressions, analyze and debug failures, and work closely with your team members to resolve issues efficiently and improve overall design quality.

The ideal candidate combines strong technical rigor with creativity and adaptability, thrives in a fast-paced multidisciplinary environment, and is motivated by contributing to breakthrough imaging technologies.

Key Responsibilities

• Define and implement digital blocks such as timing controllers, sequencers, control logic, and data-path architectures for advanced CMOS image sensor and mixed-signal ASIC products.
• Create micro-architecture specifications for digital subsystem blocks.
• Design, implement, and debug RTL logic (Verilog/VHDL/SystemVerilog) with strong attention to power, performance, and area (PPA) optimization.
• Develop low-power, high-speed digital designs optimized for image sensor performance and system integration.
• Integrate and validate 3rd-party IP blocks and standard interfaces into the digital subsystem.
• Ensure design quality through linting, STA, CDC, and robust coding methodologies.

Mixed-Signal & System Integration

• Collaborate closely with analog, pixel, modeling and system teams to ensure seamless mixed-signal integration.
• Support the setup and execution of mixed-mode simulations.
• Support calibration engines, correction algorithms, and on-chip processing functions.
• Contribute to architecture trade-offs and system-level performance optimization.

Verification, Validation & Bring-Up

• Define and implement advanced digital verification methodologies for complex image sensor ASICs.
• Develop block-level and top-level constrained-random and directed test benches.
• Create and execute functional verification plans using industry-standard simulation tools on both RTL and gate-level/netlist designs.
• Define coverage metrics and drive coverage closure activities, including setup, analysis, reporting, enhancement, and signoff.
• Implement and maintain automated regression environments and debug simulation failures efficiently.
• Define verification signoff methodologies and ensure verification completeness against specifications.
• Verify and integrate third-party IP blocks into the digital subsystem.
• Prepare detailed verification documentation, including specifications, verification plans, test protocols, and test reports.
• Implement or support Design-for-Test (DFT) methodologies including BIST, scan insertion support, vector scanning, and boundary scan support.
• Support FPGA prototyping, chip bring-up, characterization, silicon validation, and post-silicon debug activities.
• Provide support during production test development and customer/post-sales technical investigations when required.

Physical Design & Implementation Support

• Support synthesis and backend implementation activities.
• Write and maintain SDC and UPF constraint files.
• Analyze, debug, and resolve timing closure and power-related implementation issues.
• Collaborate with physical design teams to optimize floorplanning, timing, and power efficiency.

Innovation & Technical Contribution

• Participate in the development and continuous improvement of design and verification methodologies, flows, and automation/efficiency enhancements.
• Contribute to innovation, IP development, and patent generation activities.
• Stay up to date with industry standards, emerging technologies, tools, and semiconductor market trends.
• Contribute to technology evaluations, supplier assessments, and EDA tool selection.

Qualifications

Education

• Master’s or PhD in Electrical Engineering, Microelectronics, or Physics or related field.

Experience

• 7+ years of hands‑on experience in digital IC/ASIC design, preferably in CMOS image sensors or mixed‑signal SoCs.
• Proven experience in digital IC development from architecture definition through RTL implementation, verification, tape‑out, and silicon bring‑up.
• Strong experience in RTL design using Verilog and/or VHDL.
• Strong experience in SystemVerilog for verification (functional coverage, code coverage, …). Experience with assertion-based verification using SVA and/or PSL.
• Solid understanding of ASIC development flows including synthesis, STA, linting, timing closure, and low‑power design techniques.
• Hands‑on experience with simulation and debugging tools such as Cadence Xcelium/IES or Siemens EDA (Mentor Graphics) Questa.
• Experience with DFT methodologies and digital verification flows.
• Experience working in Linux‑based development environments and scripting using Python, TCL, Shell, or Perl.
• Experience with version control systems such as Git or SVN.

Preferred Skills

• Knowledge of CMOS image sensor architectures and image signal processing pipelines.
• Familiarity with high‑speed and embedded interfaces such as MIPI, LVDS, I2C, I3C, SPI….
• Experience with SystemVerilog, SystemC, C/C++, or High‑Level Synthesis tools is a plus.
• Knowledge of ASIC/CMOS fabrication technologies and physical design considerations.
• Understanding of compression algorithms and ISP architectures is a plus.
• Understanding of task estimation, planning, and development execution in collaborative engineering environments.
• Familiarity with Continuous Integration (CI) and Continuous Development/Deployment (CD) flows and associated tools.
• Experience building and maintaining automated regression environments.
• Familiarity with FPGA prototyping and debug flows.
• Experience with gate‑level simulations (GLS).
• Exposure to firmware development and firmware verification activities.
• Creative and proactive mindset with strong attention to detail.
• Effective communication and collaboration skills across multidisciplinary teams.
• Ability to thrive in a fast‑paced, innovation‑driven start‑up environment.
• Strong sense of ownership and commitment to design quality and execution.