Senior FPGA Test & Verification Engineer (SystemVerilog/C++)

GQR; Sydney; On-site; AUD 100,000 - 130,000; Full time

Job summary

A leading global technology firm in Sydney is seeking a mid-senior level Validation Engineer skilled in FPGA testing and verification. You will develop testing strategies for cutting-edge trading platforms and utilize Python and C++ in a Linux environment. Strong problem-solving skills are essential. Confidential inquiries are welcome. Apply via email for this full-time position.

Qualifications

• Prior experience in testing and verification of FPGA-based trading platforms or related hardware/software systems.
• Proficiency in Python and C++ in a Linux environment.
• Strong problem-solving skills and ability to work independently and in a team.

Responsibilities

• Develop testing and verification strategies for FPGA systems.
• Implement simulation and hardware testing for multiple exchanges.
• Ensure adherence to testing standards and methodologies.

Skills

FPGA testing and verification

SystemVerilog

Python

C++

CI/CD pipelines

Problem-solving

Job description

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