Experienced IC Design Engineer

Raspberry Pi Ltd; Town of Cambridge; Vor Ort; AUD 154.024 - 192.530; Vollzeit

Benefits dieser Stelle

Competitive salary

Employer pension contributions

Life assurance

Income protection

Private medical insurance

Electric vehicle salary sacrifice scheme

Zusammenfassung

Raspberry Pi is looking for an experienced IC Design engineer to enhance their ASIC team in Cambridge. The role involves overseeing design tasks from specifications to verification, while collaborating closely with software teams.

Key qualifications include extensive experience in SoC or MCU architecture and a strong understanding of modern processor design principles. Candidates should be comfortable with RTL, SystemVerilog, and embedded C programming.

Competitive salary and benefits like life assurance and private medical insurance are offered.

Qualifikationen

• 10+ years of experience in SoC or MCU architecture.
• Experience with modern microcontroller and processor design.
• Strong grasp of SoC concepts and implementation reality.

Aufgaben

• Design, IP integration, verification planning, and execution.
• Work closely with the software team for support.
• Assist with power and timing issues in implementation.

Kenntnisse

SoC or MCU architecture experience

Modern microcontroller and processor design

Understanding of RTL and SystemVerilog

Embedded C programming skills

Proficiency in scripting languages

Tools

Cadence simulation tools

Jobbeschreibung

Raspberry Pi is seeking an experienced IC Design engineer to join our expanding ASIC team to help deliver our next‑generation products. We have been building our own silicon at Raspberry Pi for some years now, starting with the RP2040 microcontroller in 2021, and following with the RP1 southbridge chip for the main Raspberry Pi platform on Raspberry Pi 5. Our second‑generation microcontroller, RP2350, was released in 2024. The ASIC team looks after everything in the silicon flow, from specification through design, verification, and implementation, including ATE test and qualification. With a small team, we get involved in all aspects of getting successful products into production.

As an experienced design engineer, you will take ownership of front‑end tasks from specification to design, verification, and implementation with support from specialists in other teams. You will be capable of both working autonomously and also dynamically with other members of the ASIC team. Your responsibilities will include:

• Design, IP integration, verification planning and execution
• Specifying and/or configuring IP and systems
• Working closely with the software team
• Supporting FPGA platforms for fast software development and verification
• Assisting the implementation team with power and timing issues

Key requirements

• A good level of experience (typically 10+ years) in SoC or MCU architecture, with at least one tape‑out where you held architectural ownership of a chip or non‑trivial subsystem.
• Deep understanding of modern microcontroller and processor design, including real‑time behaviour, deterministic interrupt handling, low‑power modes, flash/SRAM hierarchies, and common peripherals (e.g. SPI, I²C, UART, USB, PIO‑style fabrics, ADC/DAC, timers).
• Equally strong grasp of broader SoC concepts: coherent and non‑coherent interconnect, AXI/AHB/APB, cache hierarchies, DMA, memory controllers, security architecture (TrustZone or equivalent), and how an OS‑class subsystem coexists with real‑time domains on the same die.
• Fluent in the implementation reality of chips — RTL (SystemVerilog), verification methodology (UVM, formal, emulation/FPGA), DFT, timing closure, power analysis, and physical design constraints. You do not need to be a specialist in each, but you need to be credible across all of them.
• Track record of making good engineering trade‑offs under real cost, schedule, and PPA pressure, and communicating them clearly to both engineers and non‑engineers.
• Comfortable working close to software: you have written non‑trivial embedded C, understand toolchain and SDK implications of architectural choices, and care about what shipping the chip feels like for the developer using it.
• Ability to communicate complex ideas, design goals, and status effectively both verbally and through documentation.
• Strong drive and ability to work to a schedule.
• Familiarity with scripting languages (Bash, Python, Tcl, etc)

The following would also be useful:

• Experience of Cadence simulation tool flow.
• Experience with ASIC/FPGA synthesis and implementation, DFT architecture and insertion, software development, and scripting.

The role is based in Cambridge with an expectation of full‑time office attendance.

• Competitive salary based on level of experience
• Employer pension contributions of 8% when the employee contributes 4% of their gross salary into the salary sacrifice scheme
• Life assurance of 4 × base salary
• Income protection of 75% of base salary in the event of critical illness, commencing after 13 weeks of long‑term illness or absence from work
• Private medical insurance (medical history disregarded)
• Access to our electric vehicle salary sacrifice scheme, subject to eligibility