Design Verification Engineer - Accelerators

Meta; Redmond; On-site; AUD 259,000 - 364,000; Full time

Job summary

Meta is hiring a Design Verification (DV) lead for accelerators to own verification for complex computer vision and imaging IPs and subsystems. You will define DV strategy across IPs, build scalable DV infrastructure, and drive sign-off across multiple blocks.

We seek a senior engineer with extensive SystemVerilog/UVM/C/C++ experience, DV leadership, and a track record of tape-outs. Join a fast-moving silicon team delivering advanced AR/VR hardware.

Qualifications

• 8+ years of hands-on verification experience with SystemVerilog, UVM, and C/C++ at IP/SoC level.
• Led DV for complex IP or SoC through tape-out with sign-off ownership.
• Defined verification plans, coverage strategies, and closure metrics across multiple blocks.
• Built UVM environments from scratch and reusable verification components.
• Experience in formal verification, SVA, emulation/FPGA prototyping, or UPF.
• Strong scripting in Python, TCL, Perl, and Shell for tools/flows.
• Led and mentored engineers across teams.

Responsibilities

• Shape architecture and microarchitecture decisions with cross-functional teams to ensure verif-friendly design.
• Own DV for multiple IPs/subsystems from planning to sign-off.
• Define strategy across IPs including simulation, formal, assertions, emulation, and UPF.
• Design reusable testbenches, DV IPs and libraries shared across IPs.
• Drive regression management, triage, coverage analytics, and efficient runs.
• Spot DV quality gaps and lead methodology improvements including AI-assisted ones.
• Root-cause failures to RTL, reference model or FW/SW and propose fixes.

Skills

SystemVerilog

UVM

C/C++

DV leadership

Verification planning

Coverage metrics

UVM from scratch

Formal verification

SVA

Emulation/FPGA prototyping

UPF (low-power)

Python scripting

TCL

Perl

Shell scripting

Team leadership

Education

Master's or PhD in EE/CE/CS

Job description

Summary:

The AR glasses Meta is building run on custom silicon that delivers serious compute within a tight power budget. Our silicon team designs that silicon, with breakthrough work in computer vision, machine learning, imaging, and sensing. We're hiring a Design Verification (DV) lead to own verification for complex computer vision and imaging accelerator IP and subsystems. In this role, you'll define the verification strategy across multiple IPs and build DV infrastructure that scales across chips and programs.

Required Skills:

Design Verification Engineer - Accelerators Responsibilities:

1. Shape architecture and microarchitecture decisions with architects, design, FW/SW, emulation, physical design and post-silicon teams so the chip is designed with verification in mind. Work with TPMs on schedules and sign-off criteria

2. Own DV for multiple complex IPs or subsystems from start to finish, all the way from verification planning through coverage closure and sign-off

3. Define the strategy across IPs, including the mix of simulation (constrained-random, UVM), formal, assertions, emulation and FPGA prototyping, plus power-aware verification (UPF)

4. Design reusable testbench architectures, verification IP and libraries that are shared across IPs, subsystems and SoC generations

5. Drive regression management, automated triage, coverage analytics, and compute-efficient runs (simulation and emulation) so the team can sustain high throughput as the number of designs grows

6. Spot verification-quality and productivity gaps across the org, lead initiatives that measurably improve quality and time-to-closure, and drive DV methodology improvements, including AI-assisted ones

7. Root-cause failures down to specific lines of RTL, reference model or FW/SW, and propose the fixes

Minimum Qualifications:

Minimum Qualifications:

1. 8+ years of hands-on verification experience with SystemVerilog, UVM and C/C++ at the IP, subsystem and SoC level

2. Has led DV for complex IP or an SoC through tape-out, including owning sign-off

3. Has defined and run verification plans, coverage strategies, and closure metrics (functional and code coverage) across multiple blocks or IPs

4. Has built UVM verification environments from scratch and designed reusable verification components

5. Deep experience in at least one of: formal verification, SystemVerilog Assertions (SVA), emulation/FPGA prototyping, or low-power (UPF) verification

6. Strong scripting skills (Python, TCL, Perl, Shell) for building verification tools and flows

7. Has led and mentored engineers and coordinated work across teams

Preferred Qualifications:

Preferred Qualifications:

1. Has verified power-limited mobile, wearable or AR/VR System-on-Chips (SoCs)

2. Has managed EDA vendors or contracted DV teams

3. Has verified computer vision, imaging/ISP, DSP or ML accelerator designs

4. Master's or PhD in EE/CE/CS

5. Has rolled out methodology changes (formal, emulation, portable stimulus, ML/AI-assisted verification) across an org

6. Has verified hardware against reference models written in C++ or Python, or co-simulated with firmware or software

7. Has scaled DV infrastructure (regression farms, CI for hardware, coverage and triage dashboards) across multiple IPs or programs

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affiantional Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].