Staff Hardware Board Design Engineer

Evollabs; Dubai; On-site; AED 320,000 - 520,000; Full time

Job summary

Evollabs in Dubai is seeking a Staff Hardware Board Design Engineer to own board architecture for AI accelerator platforms, from initial test PCB to production cards powering data centers. You will translate silicon and system requirements into schematics, power trees, and high-speed interfaces, drive layout decisions, and lead lab bring-up, characterization, and debug with cross-functional teams.

Join a fast-moving, hands-on team where you mentor engineers and shape the platform that enables

Qualifications

• Bachelor’s or Master’s in Electrical Engineering or related field.
• 10+ years of board-level hardware design experience for compute/accelerator products.
• Proven ownership of schematic capture and board architecture.
• Hands-on experience with PCIe Gen4+/high-speed interfaces and DDR/LPDDR/GDDR.
• Strong power electronics design: multi-phase VRM, PDN impedance, decoupling and telemetry.

Responsibilities

• Define board-level architecture and own schematic capture for AI accelerator cards and system boards.
• Design and evaluate test PCBs for silicon bring-up, providing JTAG, probes, and instrumentation.
• Design multi-rail power delivery networks and manage impedance constraints for high-speed links.
• Plan lab bring-up, characterization, margining, and root-cause analysis across hardware, firmware, and silicon.
• Drive DFM/DFT/DFx reviews, BOM management, and vendor coordination through to production.
• Write specifications, reviews, and bring-up/test plans; mentor engineers and align teams.

Skills

Board architecture

Schematic capture

High-speed interfaces

Power electronics

Lab bring-up

Python scripting

Technical leadership

Cross-functional communication

Education

Bachelor’s or Master’s in Electrical Engineering

Tools

Cadence Allegro System Capture

OrCAD Capture

Altium Designer

Job description

Team: Hardware Engineering – Board Design & Bring-Up

Type: Full-time – On-site

About Us

We are a tech company specializing in the design and development of cutting-edge, customizedserver hardware solutions optimized for artificial intelligence and machine learning applications.Our mission is to empower businesses and researchers to accelerate their AI initiatives byproviding them with high-performance, scalable, and energy-efficient hardware infrastructure.

As a rapidly growing company at the forefront of AI hardware innovation, we are constantlyseeking talented and motivated individuals to join our team. We offer a dynamic and challengingwork environment, with opportunities to make a significant impact on the future of AI technology.

Your Mission

As a Staff Hardware Board Design Engineer, you will be the electrical design authority for theboards that carry our AI accelerator silicon, from the first test PCB that powers up a new chip tothe production accelerator card or module that ships in a data center rack. You will set board-level architecture, translate silicon and system requirements into schematics, power trees, andhigh-speed interface budgets, define the constraints that drive layout, and take the resultinghardware through lab bring-up, characterization, and debug. You will own board programs endto end and be the person the silicon, firmware, and validation teams come to when the platformhas to work.

Responsibilities

• Accelerator board architecture and schematic design: set board-level architectureand own schematic capture for AI accelerator cards, modules, and system boards,including component selection, clocking and reset topologies, sideband managementinterfaces, and connector and form-factor decisions.
• Test PCB design for silicon bring-up: design the evaluation, characterization, andsocketed test boards used to power up and qualify new chips, providing programmablerails and current sensing, clean clock sources, JTAG and scan access, probe andinstrumentation points, thermal fixturing, and package breakout structures that make firstsilicon observable and debuggable.
• Power delivery network design: design high-current, multi-rail power trees foraccelerator-class devices, covering multi-phase VRM selection and compensation, PDNimpedance targets, decoupling strategy, power sequencing and telemetry over PMBus,and protection and hot-swap behaviour. High-speed interface budgets and layout direction: define stackup, material,impedance, and routing constraints for PCIe Gen5 and Gen6, DDR5, LPDDR5, GDDR6and GDDR7 or HBM-adjacent interfaces, 100G to 800G Ethernet, and die-to-die andSerDes links, then drive layout execution with our in-house PCB layout and signal andpower integrity engineers as well as external layout partners.
• Lab bring-up, characterization, and debug: plan and execute board and silicon bring-up, run electrical characterization and margining, and root-cause failures across thehardware, firmware, and silicon boundary using oscilloscopes, high-bandwidth probes,BERTs, VNAs, protocol and power analyzers, and thermal imaging.
• Manufacturing readiness and vendor execution: drive DFM, DFT, and DFA reviews,prototype and NPI builds, ECO and BOM management, and compliance activities withfabricators, assembly houses, ODMs, and contract manufacturers through to volumeproduction.
• Technical leadership and documentation: write board specifications, schematicreview packages, bring-up and test plans, and errata, act as design authority in reviews,align silicon, package, firmware, thermal, mechanical, and validation teams around asingle platform definition, and mentor engineers as the board team grows.

Requirements

• Bachelor’s or Master’s in Electrical Engineering, Electronics Engineering, or related field.
• 10+ years of board-level hardware design experience with a strong focus on high-speeddigital boards for compute, networking, or accelerator products, including at least oneplatform owned end to end from concept through volume production and at least onefirst-silicon bring-up.
• Proven ownership of schematic capture and board architecture in a professional ECADflow such as Cadence Allegro System Capture, OrCAD Capture, or Altium Designer.
• Hands-on experience designing and debugging high-speed interfaces such as PCIeGen4 or newer, DDR4 or DDR5, LPDDR, GDDR, or multi-gigabit SerDes and Ethernetlinks, including how loss, crosstalk, and return-path decisions shape the schematic andstackup.
• Strong power electronics competence at board level: multi-phase VRM design, high-current PDN design, decoupling and target impedance analysis, power sequencing, andtelemetry.
• Demonstrated silicon or board bring-up experience: taking untested hardware from firstpower-on to functional and characterized, and driving issues to root cause.
• Fluency with lab instrumentation and measurement practice, including oscilloscopes andprobing technique, power and network analyzers, and protocol or bus analyzers.
• Working knowledge of low-speed management and control subsystems: I2C, SMBus,SPI, UART, JTAG, EEPROM and FRU handling, BMC or MCU based boardmanagement, and reset and sequencing logic.
• Practical command of DFM, DFT, and DFA, PCB fabrication and assembly processes,and design release packages, with experience working directly with fab and assemblyvendors.
• Proficiency with Python or equivalent scripting for lab automation, data capture, andmeasurement post-processing.
• Demonstrated technical leadership: acting as design authority in schematic and layoutreviews, steering external layout houses, ODMs, and component vendors, andmentoring less experienced engineers.
• Excellent cross-functional communication and documentation skills, with the ability tolead design reviews and to drive alignment with silicon, firmware, mechanical, andmanufacturing partners.

Preferred Qualifications (Nice-to-Haves)

• Experience with AI accelerator or GPU form factors such as OAM and UBB, SXM, PCIeCEM cards, or OCP and DC-MHS compliant platforms, including liquid-cooled designs.
• Signal and power integrity simulation experience with tools such as Cadence Sigrity,Ansys HFSS or SIwave, Keysight ADS, or HyperLynx, and the ability to interpret and acton extraction results.
• Silicon and package co-design exposure: BGA escape planning, substrate and 2.5D orHBM package constraints, and joint debug with package and ASIC teams.
• Post-silicon characterization experience including voltage and frequency margining andcorrelating lab measurements with ATE or emulation results.
• Familiarity with FPGA prototyping platforms, socketed test boards, and interposer orriser based debug hardware.
• Experience with thermal and mechanical co-design for high-power boards, including coldplates, heatsink loading, and board stiffening.

Why Join Us

• Own the physical platform that our AI silicon runs on, where your board decisionsdirectly determine whether the chip meets its performance, power, and reliability targets.
• Work shoulder to shoulder with silicon, package, firmware, and validation engineers in a fast-moving team that values hands-on depth and measurement over guesswork.
• Build hardware end to end, from the first bring-up fixture on a lab bench to a productionaccelerator platform, with real authority over architecture, vendor, and technologychoices, and the scope to shape the board team as it grows.
• Competitive compensation, growth opportunities, and the chance to help define theplatform that powers advanced AI workloads.

Ready to Accelerate the Future of AI?

If you’re passionate about turning new silicon into working, measurable, manufacturable hardware — we’d love to hear from you.