High-Speed PCB Layout Engineer

Evollabs; Dubai; On-site; AED 420,000 - 540,000; Full time

Job summary

Evollabs in Dubai is seeking an experienced High-Speed PCB Layout Engineer to own multi-layer AI accelerator boards from floorplanning to routing and release. You will manage tight impedance budgets, HDI processes, and high‑current PDN layouts in a production-grade environment.

The role requires strong Cadence Allegro skills, 16+ layer boards, and coordination with SI/PI, mechanical, and fab teams to deliver manufacturable, testable boards on schedule.

Qualifications

• Diploma or degree in Electrical/Electronics Engineering.
• 8+ years of high-speed, high-density PCB layout experience.
• Proficient in Cadence Allegro; Altium Designer or Siemens Xpedition is a plus.
• Proven track record laying out high-layer-count boards (16 layers+), using HDI, via-in-pad, VIPPO, blind/buried vias.
• Ability to route PCIe Gen5/6, LPDDR5, GDDR6/7, and 400G/800G Ethernet interfaces.
• Experience with escape routing from large, fine-pitch BGA packages and dense land grid footprints.
• Knowledge of stackup, impedance, loss budgets, and fabrication tolerances impact on channel performance.
• Experience collaborating with SI/PI, mechanical, and fab teams; conducting DFM/DFT reviews.

Responsibilities

• Own end-to-end multi-layer PCB layouts for AI accelerator boards and test fixtures.
• Execute ASIC package escape routing and high-speed channels routing.
• Define stackups, impedance targets, and material choices with fabricators.
• Manage constraint sets, timing closure, and differential pair tuning in Cadence Allegro Constraint Manager.
• Design high-current PDN layouts with proper decoupling and thermal vias.
• Iterate layout based on signal and power integrity analyses with SI/PI engineers.
• Prepare complete release packages in Gerber/ODB++/IPC-2581.

Education

Bachelor's in Electrical Engineering

Tools

Cadence Allegro

Allegro Constraint Manager

Altium Designer

Siemens Xpedition

Cadence Sigrity

PowerSI

HFSS

Job description

Team: Hardware Engineering – PCB Layout & Signal Integrity

Type: Full-time – On-site

About Us

We are a tech company specializing in the design and development of cutting‑edge, customized‑server hardware solutions optimized for artificial intelligence and machine learning applications. Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high‑performance, scalable, and energy‑efficient hardware infrastructure. As a rapidly growing company at the forefront of AI hardware innovation, we are constantly seeking talented and motivated individuals to join our team. We offer a dynamic and challenging work environment, with opportunities to make a significant impact on the future of AI technology.

Your Mission

As a High‑Speed PCB Layout Engineer, you will own the physical realization of our AI accelerator boards: the stackups, the escape routing out of large fine‑pitch ASIC packages, the multi‑gigabit channels, and the high‑current power shapes that decide whether a design closes its loss and impedance budgets. You will work from schematics and constraint sets owned by our board design engineers and turn them into dense, manufacturable, high layer count PCBs, spanning both production accelerator platforms and the test boards used for silicon bring‑up and characterization.

Responsibilities

• High‑density board layout ownership: own multi‑layer PCB layouts end to end for AI accelerator cards, modules, system boards, and silicon test fixtures, from floorplanning and placement through routing, copper pour, and release.
• ASIC package escape and high‑speed routing: execute escape routing for large, fine‑pitch BGA and route multi‑gigabit channels including PCIe Gen6, GDDR7, and 400G/800G Ethernet links, applying HDI, via‑in pad and VIPPO, blind and buried vias, backdrilling, and any‑layer interconnect where needed.
• Stackup, impedance, and material definition: define and negotiate layer stackups, dielectric materials, impedance targets, and loss budgets with fabricators, and select constructions that meet electrical, thermal, and cost objectives.
• Constraint management and timing closure: build and maintain constraint sets in Cadence Allegro Constraint Manager, including differential pair phase tuning, delay and skew matching, T‑topologies, Z‑axis delay compensation, crosstalk control, and return‑path continuity.
• Power distribution layout: lay out high‑current power delivery for accelerator‑class devices, covering plane and shape partitioning, copper weight and thermal via strategy, decoupling placement, and PDN loop inductance minimization in coordination with power integrity engineers.
• Simulation‑driven iteration: work with signal and power integrity engineers to extract critical channels and planes, interpret results, and iterate placement, stackup, and routing until the design meets its margins.
• Manufacturability and release: drive DFM, DFA, and DFT reviews with fab and assembly vendors, maintain footprint and padstack libraries and ECAD data integrity, and produce complete, unambiguous release packages in Gerber, ODB++, or IPC‑2581.

Requirements

• Diploma, Bachelor’s, or equivalent qualification in Electrical or Electronics Engineering, or equivalent professional PCB design experience.
• 8+ years of high‑speed, high‑density PCB layout experience, with a strong focus on server, networking, or AI accelerator hardware.
• Expert‑level proficiency in Cadence Allegro including Constraint Manager; Altium Designer or Siemens Xpedition experience is a plus.
• Proven track record laying out high layer count boards, ideally 16 layers and above, using HDI, sequential lamination, via‑in‑pad and VIPPO, blind and buried vias, and controlled‑depth backdrilling.
• Demonstrated routing of at least two of the following interface families to closure: PCIe Gen5/6, LPDDR5, GDDR6/7, HBM‑adjacent interfaces, 400G/800G Ethernet.
• Hands‑on experience with escape routing from large, fine‑pitch BGA packages and dense land grid footprints.
• Solid grasp of stackup and material selection, impedance control, insertion loss budgeting, and how fabrication tolerances affect real channel performance.
• Competence in high‑current power plane layout, thermal via and copper weight decisions, and decoupling placement for PDN performance.
• Working knowledge of IPC standards including IPC‑2221, IPC‑2222, IPC‑6012, and IPC‑7351, plus practical DFM, DFA, and DFT rule sets from real production builds.
• Experience collaborating with signal and power integrity engineers, mechanical designers, and fabricators, including running layout and DFM reviews directly with vendors.
• Strong communication and documentation skills, with the discipline to keep libraries, constraints, revisions, and release data clean and traceable.

Preferred Qualifications (Nice‑to‑Haves)

• Automation and scripting experience with Allegro SKILL or equivalent to accelerate repetitive layout and checking tasks.
• Direct use of extraction and simulation tools such as Cadence Sigrity and PowerSI, Ansys SIwave or HFSS, or Clarity, and the ability to close loops without waiting on a specialist.
• Experience with AI accelerator and data center form factors such as OAM, UBB, SXM, PCIe CEM, or OCP and DC‑MHS compliant boards, including liquid‑cooled and cold‑plate constrained layouts.
• Rigid‑flex, press‑fit connector, cable, and backplane or midplane layout experience.
• Mechanical co‑design fluency with STEP exchange and tools such as SolidWorks, Creo, or NX for tightly packaged, high‑power assemblies.

Why Join Us

• Route the boards that carry our own AI silicon, where your stackup and escape strategy decisions directly set the performance ceiling of the product.
• Sit inside the engineering team rather than at the end of a handoff chain, working daily with board design, signal integrity, package, and mechanical engineers.
• Take on genuinely hard layout problems, from dense ASIC package escapes to first‑of‑a‑kind bring‑up fixtures, with the tooling and vendor access to do them properly.
• Competitive compensation, growth opportunities, and the chance to help define the platform that powers advanced AI workloads.