RTL Developer (Dubai Office)

Evollabs Tech; Dubai; On-site; AED 300,000 - 540,000; Full time

Job summary

Evollabs Tech seeks a senior RTL/ASIC engineer to own end-to-end design of critical subsystems, from PLLs to interconnects, delivering production silicon for AI workloads. You will work with silicon architects and verification teams to ensure fast, power-efficient hardware that scales with AI workloads.

The role requires strong HDL skills (Verilog/SystemVerilog), IP integration experience, and expertise in DFT, timing closure, and high-speed interfaces like PCIe/UCIe. On-site in Dubai, UAE.

Qualifications

• 7+ years of RTL design and ASIC development.
• Experience with architecture trade-offs and producing interface specs.
• Experience with multiple clock domains and AMBA protocols.

Responsibilities

• Own complex ASIC subsystems end-to-end from spec to post-silicon validation.
• Write production-quality RTL (Verilog/SystemVerilog) and define interfaces.
• Verify at block and subsystem levels (UVM/formal).
• Develop constraints and close timing: SDC/STA; CDC/RDC analysis.
• Simulate and emulate (FPGA/emulator); debug waveforms/logs.
• Define and implement DFT/DFD (JTAG, MBIST/LBIST).
• Maintain lint, CDC/RDC, LEC; drive ECOs.
• Build timing/debug automation using Tcl/PrimeTime.

Skills

RTL design

ASIC development

Verilog

SystemVerilog

Clock domain crossing

IP integration

AMBA protocols

High-speed interfaces

Tools

PrimeTime

UVM

Formal verification

Synthesis

Job description

Your Mission

Own the end-to-end design of critical ASIC subsystems-from PLLs and compute clusters to interconnects and multi-die orchestration. The RTL you build becomes production silicon and moves real AI workloads faster. This is where microseconds, watts, and millimeters directly impact AI economics at scale.

Responsibilities

• Own complex ASIC subsystems end-to-end: specification, architectural exploration, IP evaluation/selection, integration, verification planning, and post-silicon validation
• Make architecture/micro-architecture trade-offs across features, performance, power, and area; define clean interfaces and write production-quality RTL (Verilog/SystemVerilog).
• Implement and verify at block and subsystem levels (UVM/formal where appropriate); set coverage goals and drive sign-off.
• Develop constraints and close timing: author SDC, run STA (setup/hold, OCV/derates), perform CDC/RDC analysis, and collaborate with PD on floorplanning and CTS.
• Simulate and emulate (FPGA/emulator), debug waveforms/logs, and correlate pre-/post-silicon behavior.
• Define and implement DFT/DFD (scan, MBIST/LBIST, boundary scan/JTAG); support ATPG and test bring-up.
• Maintain code quality with lint, CDC/RDC, LEC, and synthesis-friendly design practices; drive ECOs as needed.
• Build timing/debug automation: create Tcl/PrimeTime scripts for skew analysis, clock dividers/special clocks, and core-to-IO interfaces (PCIe, 400GE, UCIe).
• Document clearly: specifications, micro-architecture, interfaces, and user guides for downstream teams.

You’ll Collaborate With

Our silicon architects designing the next breakthrough in AI compute, verification engineers, Linux driver and firmware engineers building the software stack, security teams protecting customer assets, compiler and ML framework teams optimizing workload mapping, and system validation engineers ensuring enterprise reliability — together, we’re building the infrastructure that makes AI accessible and powerful.

Minimum Qualifications

• 7+ years of experience in RTL design and ASIC development (verilog/systemverilog is preferred)
• Hands-on experience in all aspects of the chip development process with proficiency in front end tools and methodologies
• Experience with configuration and integration of a complex IPs is a must (at least one of the following: multi-core CPUs, NOCs, custom accelerators aka GPU/NPU or high-speed interfaces like PCIe, 100/400G Ethernet, UCIe)
• Experience writing specifications and converting them into design
• Experience with multiple clock domains and asynchronous interfaces
• Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)

Preferred (Nice-to-Haves)

• Experience with power and clock management designs
• Formal Equivalency Checking RTL to Netlist
• Experience with DFT
• Understanding of AI accelerator architectures (systolic arrays, dataflow, tiling) and memory bandwidth optimization
• Experience with HBM/GDDR integration or other high-bandwidth memory subsystems

What Success Really Means

• First silicon boots and runs real AI workloads (not just benchmarks)
• PPA targets met: performance/watt competitive with industry leaders
• Compiler team can generate efficient code without hardware workarounds

Join us in our mission to democratize AI compute — where your RTL expertise becomes the bedrock of tomorrow's AI breakthroughs.