Wireless Radio Verification Engineer

Apple; San Diego (CA); On-site; USD 123,000 - 214,000; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Discounted products and free services

Tuition reimbursement

Relocation assistance

Bonus potential

Job summary

Apple's Wireless Connectivity team is developing state-of-the-art WiFi SoCs powering hundreds of millions of Apple products worldwide. As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through sophisticated testbenches, coverage strategies, and multi‑gigabit wireless tech—from concept to production.

You will verify radio digital controllers with RF subsystems, build UVM environments, and collaborate with Design, RF, PHY, and Systems teams.

Qualifications

• Bachelor's degree required.
• Experience with SystemVerilog/UVM verification.
• Strong problem solving and collaboration skills.

Responsibilities

• Verify Radio digital controllers or subsystems from test planning to feature closure.
• Develop UVM testbench environments and infrastructure for radio control datapath subsystems.
• Implement constrained random scenarios exercising radio protocols and control sequences.
• Collaborate on digital + mixed-signal verification for radio paths.
• Track regressions, debugging, and address coverage gaps.
• Partner with Design, RF, and Systems teams to define verification strategy.

Skills

Digital verification

UVM

SystemVerilog

Python

Education

Bachelor's degree

Tools

UVM testbench

Verilog

VHDL

Job description

Join Apple's Wireless Connectivity team developing state-of-the-art WiFi SoCs that power hundreds of millions of Apple products worldwide. You'll be part of our vertically integrated organization shaping next-gen wireless technology from concept through production. As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through sophisticated testbenches, comprehensive scenarios, and cutting-edge verification methodologies-enabling multi-gigabit wireless technology connecting the world!

Description

As a Wireless Radio Verification Engineer, you'll verify Radio digital controllers combined with RF subsystems that enable exceptional wireless performance. You'll develop verification environments for complex radio control / transceiver paths spanning PLLs, DAC / ADC data paths, power management, and co-existence mechanisms. This role emphasizes digital verification while bridging to RF/analog domains-you'll work closely with Design, RF, PHY, and Systems teams to understand radio specifications and develop comprehensive test strategies. You'll own subsystem verification from test planning through coverage closure, building testbench components and scenarios that exercise complex radio control sequences and operating modes.

Responsibilities

• Verify Radio digital controllers or subsystems from test planning, environment bring‑up, through feature closure.
• Develop UVM testbench environments, bus functional models, and infrastructure for radio control and datapath subsystems.
• Implement constrained random scenarios exercising radio protocols, control sequences, and state machine interactions.
• Collaborate on digital + mixed‑signal verification using SystemVerilog analog behavioral and/or DMS/real‑number models to validate radio control paths.
• Drive closure by tracking regressions, debugging issues, and addressing coverage gaps.
• Partner with cross‑functional Design, RF, and Systems teams to define verification strategy.
• Develop Python automation supporting verification flows and regression infrastructure.

Preferred Qualifications

• Experience with digital controllers, subsystems, or data paths.
• Experience with constrained random testing, functional coverage implementation, UVM methodology, and assertion‑based verification.
• Exposure to mixed‑signal modeling concepts including real‑number modeling.
• Exposure to RF/analog system design such as LNAs, Mixers, PLLs, amplifiers, LDOs, DAC / ADCs.
• Proficiency with Python, Perl, Bash or similar scripting for automation.
• Great teammate with excellent communication skills and desire to seek diverse technical challenges.

Minimum Qualifications

• Minimum requirement of a bachelor's degree.
• Understanding of ASIC verification flows with SystemVerilog including UVM testbench development, scenario creation, and RTL simulation.
• Experience developing verification environments, bringing up designs in simulation, and debugging functional issues.
• Experience with digital design fundamentals Verilog or VHDL.
• Experience with scripting languages such as Python, or similar.
• Strong problem‑solving abilities and collaborative approach to engineering challenges.

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $122,700 and $214,300, and your base pay will depend on your skills, qualifications, experience, and location.

You’ll also receive benefits including:

• Comprehensive medical and dental coverage
• retirement benefits
• a range of discounted products and free services
• and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition

Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.

Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.