Tech Lead Physical Design Engineer, Power Integrity

Astera Labs; Santa Clara (CA); On-site; USD 160,000 - 200,000; Full time

Job summary

Astera Labs is scaling the connectivity fabric behind the world's largest AI clusters, and reliable power delivery is non-negotiable in the SoCs we ship. As a Technical Lead Physical Design Engineer- Power Integrity, you will own IR drop and electromigration analysis and closure across Astera Labs' connectivity ASIC portfolio, driving power integrity from early floorplan through tapeout.

You will partner with power grid, floorplan, package, and implementation teams to ensure stable power

Qualifications

• 5+ years in IR drop, EM analysis and power integrity sign-off for advanced SoCs.
• Proficient with Cadence Voltus and Synopsys EM tools; power grid expertise.
• Experience in UPF-based power domain planning and multi-voltage sign-off.

Responsibilities

• Own IR drop and EMIR analysis from floorplan to tapeout.
• Collaborate with package, floorplan and verification teams to fix hotspots.
• Develop EMIR runsets and dashboards to improve predictability.
• Deliver root-cause analysis with remediation guidance.

Skills

Tcl scripting

Python scripting

Perl scripting

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree (preferred)

Tools

Cadence Voltus

Synopsys RedHawk-SC

PrimeTime PX

Job description

Tech Lead Physical Design Engineer, Power Integrity

San Jose, California, United States

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Role Overview

Astera Labs is scaling the connectivity fabric behind the world's largest AI clusters, and reliable power delivery is non-negotiable in the SoCs we ship. As a Technical Lead Physical Design Engineer- Power Integrity, you will own IR drop and electromigration (IR/EMIR) analysis and closure across Astera Labs' connectivity ASIC portfolio, driving power integrity from early floorplan through tapeout.

You will partner closely with power grid, floorplan, package, and implementation teams to ensure stable power delivery, meet foundry sign-off criteria, and prevent long-term reliability issues in production silicon. This role is fully on-site at our San Jose, CA location.

Key Responsibilities

• Power Integrity Analysis & Sign-off
  • Own static and dynamic IR drop and electromigration analysis at block and full-chip levels, driving closure to foundry sign-off criteria
  • Drive UPF-based power domain planning and power-aware sign-off across multi-voltage designs
  • Analyze thermal and current density issues and recommend design modifications to ensure long-term reliability
• Design Convergence & Cross-Functional Partnership
  • Collaborate with package, power grid, and floorplan teams to identify and resolve voltage drop hotspots and EM violations early in the design cycle
  • Provide actionable feedback to implementation teams on power grid reinforcement, decap strategy, and hard-macro / SerDes integration
  • Partner with RTL, STA, verification, IP vendors, and foundry to drive power integrity convergence through tapeout
• Develop and refine EMIR runsets, stimulus methodologies, and reporting dashboards to improve predictability and reduce iterations
• Build and maintain EMIR analysis flows and automation infrastructure for efficient multi-corner analysis
• Deliver clear, actionable root-cause analysis and mitigation guidance at both block and full-chip levels

Basic Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of experience in IR drop, electromigration analysis, and power integrity sign-off for complex SoCs at advanced nodes (7nm and below)
• Deep expertise in power grid design, PDN analysis, and EM reliability mitigation, including static and dynamic IR methodologies and foundry sign-off criteria
• Proficiency with Cadence Voltus and/or Synopsys RedHawk-SC / PrimeTime PX
• Strong scripting ability in Tcl, Python, and/or Perl for flow automation and data analysis

Preferred Qualifications:

• Master's degree in Electrical Engineering or a related field
• Power integrity experience on high-speed SerDes, Ethernet PHY, or PCIe designs
• Package-level power delivery analysis / co-simulation, including advanced packaging or multi-die integration exposure
• Experience building EMIR methodology infrastructure that scales across multiple concurrent tapeout programs

Salary range is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.