Staff Silicon Validation Engineer

Marvell Semiconductor, Inc.; California, Santa Clara (MO, CA); On-site; USD 102,000 - 155,000; Full time

Job summary

An innovative firm is seeking a skilled engineer to lead the validation of cutting-edge semiconductor technologies. This role involves working with High-Speed SerDes IPs, engaging in silicon bring-up, debugging, and firmware development. You will collaborate with cross-functional teams to ensure seamless integration and performance. With a focus on defining new products and addressing application challenges, this position offers a unique opportunity to contribute to transformative technology in a dynamic environment. If you are passionate about advancing semiconductor solutions, this is the perfect opportunity for you.

Benefits

Flexible time off

401k

Year-end shutdown

Floating holidays

Paid time off to volunteer

Qualifications

• 3+ years in silicon validation or related domain.
• Strong understanding of analog and digital circuits.

Responsibilities

• Lead the initialization, debugging, and characterization of internal IPs.
• Collaborate with teams to facilitate testing and system-level debugging.

Skills

Python programming

Analog and digital circuits

Technical report writing

Education

Master's degree in Electrical/Electronic Engineering

Master's degree in Physics

Master's degree in Applied Science

Tools

HSpice

Cadence

Oscilloscopes

Power generators

Spectrum analyzers

Network analyzers

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell's Central Engineering (CE) division is at the forefront of developing cutting-edge High-Speed SerDes (HSS) IPs, serving a diverse range of applications including Switch, Automotive, Storage, and Optics. As a pivotal component of the company, CE fuels every business unit within Marvell's ecosystem. Within this framework, the Central System Engineering (CSE) team is dedicated to validating all Marvell HSS IPs in a laboratory setting, ensuring seamless support and expedited SoC production across all business units.

What You Can Expect

• Silicon Bring-Up and Debugging: Lead the initialization, debugging, and characterization of Marvell's internal IPs, such as High-Speed SerDes, PLL/DLL, and ADCs.
• Feature Evaluation and Firmware Development: Assess and debug new PHY features, develop driver firmware, gather performance data, and address application and production challenges, particularly in SAS and PCIe products.
• Cross-Functional Collaboration: Collaborate with internal SoC, Field Application Engineering (FAE), and Automated Test Equipment (ATE) teams to facilitate testing and system-level debugging.
• Test Plan Development and Automation: Create and implement bench-level validation test plans, develop scripts to automate testing processes, generate comprehensive test reports, and author application notes.
• Product Definition and Innovation: Engage in defining new products and identifying niche opportunities that align with Marvell's strategic objectives.

What We're Looking For

• Educational Background: Master's degree in Electrical/Electronic Engineering, Physics, Applied Science, or a related technical field.

• Professional Experience: A minimum of 3 years in silicon validation or a related domain.

• Technical Proficiency:

  • Strong understanding of analog and digital circuits.
  • Proficiency in Python programming.
  • Experience in writing clear and concise technical reports.

• Preferred Qualifications:

  • Familiarity with analog integrated circuit design, including package/substrate considerations and PLL/DLL/CDR/ADC/DAC architectures.
  • Experience in high-speed I/O design and testing, particularly with electrical interface protocols such as PCIe and backplane.
  • Knowledge of pre-silicon design and verification tools, including HSpice, Cadence, and other CAD tools.
  • Proficiency in using laboratory equipment such as oscilloscopes, power generators, spectrum analyzers, and network analyzers.

This role offers a unique opportunity to work with advanced technologies in a dynamic environment, contributing significantly to Marvell's mission of delivering innovative semiconductor solutions.

Expected Base Pay Range (USD)

102,880 - 154,100, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [e-mail].

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