Staff / Principal GPU Software Engineer – Triton/CUDA Kernels & Compilers

Aurtiro; United States; Remote; USD 250,000 - 320,000; Full time

Benefits offered by this job

Equity

Annual performance bonus

Job summary

Aurtiro, a leading financial compute platform, seeks a senior hardware systems and compiler engineer to own compute kernels and low-level compilation passes for AI inference engines.

You will work at the intersection of Triton, CUDA C++, PTX/SASS assembly, and ML compiler frameworks, optimizing memory paths and instruction-level parallelism for real-time workloads. Remote/hybrid options apply in the U.S. or Canada.

Qualifications

• 6-15+ years of low-level systems, compiler architecture, or GPU infrastructure engineering experience.
• Custom Kernel Mastery: Proven track record of writing, optimizing, and deploying custom Triton and CUDA C++ kernels in production.
• Low-Level Compiler Architectures: Direct experience with ML compilers and IR frameworks (TorchInductor, Triton IR, TVM, XLA, MLIR, or PTX/SASS analysis).
• Hardware Execution Telemetry: Deep expertise using NVIDIA Nsight Compute (NCU) and Nsight Systems (Nsys) to profile stalls, pressure, and pipelines.
• Hardware Execution Optimization: Knowledge of GPU microarchitecture, Tensor Cores, memory bandwidth, Roofline, and fused operators.

Responsibilities

• Author, fuse, and optimize low-level Triton and CUDA kernels for high-throughput model execution paths.
• Build and extend low-level compiler passes to optimize compute primitives for dynamic shapes and token routing scenarios.
• Conduct rigorous hardware execution analysis (TFLOPs, cache utilization, warp execution) to push kernels toward hardware limits.

Skills

Low-level systems

Compiler architecture

GPU infrastructure

Tools

NVIDIA Nsight Compute

NVIDIA Nsight Systems

Triton

TVM

MLIR

PTX/SASS analysis

Job description

One of the largest financial compute infrastructures in the world is scaling out unified AI inference ecosystem and assembling an elite team to build and optimize low-level compiler architectures and custom compute primitives. The engineering culture values deep technical rigor, where squeezing maximum hardware efficiency out of our compute fleet directly impacts global real-time infrastructure.

The Role

This is a hardcore hardware systems and compiler engineering role. You will own the compute kernels and low-level compilation passes that power our core AI inference engines. You will work at the intersection of Triton, CUDA C++, PTX/SASS assembly, and ML compiler frameworks, optimizing memory execution paths, instruction-level parallelism, and speed-of-light metrics. This role requires a specialist who naturally operates in low-level profiling tools and compiler intermediate representations (IR), not general backend optimization.

Technical Qualifications

• 6-15+ years of low-level systems, compiler architecture, or GPU infrastructure engineering experience.
• Custom Kernel Mastery: Proven track record of writing, optimizing, and deploying custom Triton and CUDA C++ kernels in production.
• Low-Level Compiler Architectures: Direct experience working with ML compilers and IR frameworks (TorchInductor, Triton IR, TVM, XLA, MLIR, or PTX/SASS analysis).
• Hardware Execution Telemetry: Deep expertise utilizing NVIDIA Nsight Compute (NCU) and Nsight Systems (Nsys) to profile instruction stalls, register pressure/spilling, shared memory bank conflicts, and TMA/cp.async pipelines.
• Hardware Execution Optimization: Deep knowledge of modern GPU microarchitecture, Tensor Cores, memory bandwidth constraints (Roofline analysis / % of SOL), and fused operators (e.g., FlashAttention, custom quantization FP8/AWQ).

Key Responsibilities

• Author, fuse, and optimize low-level Triton and CUDA kernels for high-throughput model execution paths.
• Build and extend low-level compiler passes to automatically optimize compute primitives for dynamic shapes and token routing scenarios.
• Conduct rigorous hardware execution analysis (TFLOPs, cache line utilization, warp execution) to drive kernel efficiency to theoretical hardware limits.
• Location: U.S. or Canada (Remote or Hybrid)
• Experience Level: Staff / Principal (8-15+ years)
• Base Compensation: $250,000 - $320,000 + Meaningful Equity + Annual Performance Bonus