Staff Mixed Signal Verification Engineer

Renesas Electronics; Chandler (AZ); On-site; USD 140,000 - 170,000; Full time

Benefits offered by this job

Competitive benefits

Job summary

Renesas Electronics seeks an experienced Mixed-Signal Verification Engineer to verify and model PMICs, battery chargers, and related analog IP. You will lead chip-level verification using AMS/DMS methods, integrating analog models with digital RTL/UVM environments.

You will develop verification plans, drive coverage, and own debugging across design, modeling, and verification teams, while collaborating with CAD and system architects to improve verification quality.

Qualifications

• 8-12+ years of experience in mixed-signal verification, AMS/DMS simulation, or related semiconductor design activities.
• Experience with PMICs, battery chargers, switching regulators, or power-management IP is highly desirable.

Responsibilities

• Verify and model mixed-signal power management devices including PMICs, battery chargers, and related analog IP.
• Lead chip-level verification using AMS/DMS methodologies and integrate analog behavioral models with digital RTL/UVM environments.
• Develop verification plans with traceability from requirements through coverage closure and tapeout sign-off.
• Own debugging and root-cause analysis of mixed-signal verification issues across teams.
• Collaborate with analog/digital designers, system architects, and CAD teams to improve modeling accuracy and verification quality.
• Participate in design reviews and optimize topology from a verification perspective.

Skills

Mixed-signal verification

AMS/DMS verification

Communication and collaboration

Education

B.S./M.S. Electrical Engineering

Tools

Cadence Xcelium

Spectre

SystemVerilog

Verilog-AMS

UVM

Job description

Job Description

• As a Mixed-Signal Verification Engineer, you will be responsible for the verification and modeling of mixed-signal power management devices, including PMICs, battery chargers, switching regulators, and related analog IP. You will work closely with design, systems, verification, CAD, and customer teams to drive successful development, integration, and sign-off of complex mixed-signal power chips.
• Verification: Lead chip-level verification of analog and mixed-signal circuits using AMS and DMS methodologies, integrating analog behavioral models with digital RTL and UVM-based environments. Develop verification strategies, drive coverage closure, and support product tapeout milestones.
• Modeling: Create, maintain, and validate behavioral models using SystemVerilog RNM and Verilog-AMS, translating circuit and system requirements into high-performance models suitable for both AMS co-simulation and full-chip DMS verification. Ensure model accuracy through correlation against specifications and schematic references across operating conditions.
• Verification Plan Development: Develop and execute comprehensive verification and modeling plans with full traceability from design requirements through coverage closure and tapeout sign-off. Track verification readiness and proactively identify risks to product schedules.
• Debugging: Own debug and root-cause analysis of mixed-signal verification issues, including failing test cases, model inaccuracies, analog-digital interface problems, convergence issues, and simulation performance bottlenecks. Drive resolution across design, modeling, and verification teams.
• Technical Leadership & Collaboration: Partner with analog and digital designers, system architects, verification engineers, and CAD teams to improve modeling accuracy, simulation efficiency, and verification quality. Participate in architecture and design reviews, influencing design decisions to improve verification effectiveness and reduce project risk.
• Design Review & Optimization: Participate in design reviews to evaluate circuit topology and design partitioning from a verification and modeling perspective, recommending architectural choices that simplify behavioral modeling, improve simulation convergence, and reduce verification risk. Support silicon validation and root-cause analysis of complex system-level issues by correlating simulation predictions to bench measurements.
• Documentation: Document verification plans, model validation methodologies, coverage results, and sign-off metrics to ensure clear communication and traceability throughout the product lifecycle.
• Customer Interaction: Interface directly with external customers to present verification status, review coverage results, address technical questions, and ensure verification deliverables meet product and customer requirements.

ob Description

• As a Mixed-Signal Verification Engineer, you will be responsible for the verification and modeling of mixed-signal power management devices, including PMICs, battery chargers, switching regulators, and related analog IP. You will work closely with design, systems, verification, CAD, and customer teams to drive successful development, integration, and sign-off of complex mixed-signal power chips.
• Verification: Lead chip-level verification of analog and mixed-signal circuits using AMS and DMS methodologies, integrating analog behavioral models with digital RTL and UVM-based environments. Develop verification strategies, drive coverage closure, and support product tapeout milestones.
• Modeling: Create, maintain, and validate behavioral models using SystemVerilog RNM and Verilog-AMS, translating circuit and system requirements into high-performance models suitable for both AMS co-simulation and full-chip DMS verification. Ensure model accuracy through correlation against specifications and schematic references across operating conditions.
• Verification Plan Development: Develop and execute comprehensive verification and modeling plans with full traceability from design requirements through coverage closure and tapeout sign-off. Track verification readiness and proactively identify risks to product schedules.
• Debugging: Own debug and root-cause analysis of mixed-signal verification issues, including failing test cases, model inaccuracies, analog-digital interface problems, convergence issues, and simulation performance bottlenecks. Drive resolution across design, modeling, and verification teams.
• Technical Leadership & Collaboration: Partner with analog and digital designers, system architects, verification engineers, and CAD teams to improve modeling accuracy, simulation efficiency, and verification quality. Participate in architecture and design reviews, influencing design decisions to improve verification effectiveness and reduce project risk.
• Design Review & Optimization: Participate in design reviews to evaluate circuit topology and design partitioning from a verification and modeling perspective, recommending architectural choices that simplify behavioral modeling, improve simulation convergence, and reduce verification risk. Support silicon validation and root-cause analysis of complex system-level issues by correlating simulation predictions to bench measurements.
• Documentation: Document verification plans, model validation methodologies, coverage results, and sign-off metrics to ensure clear communication and traceability throughout the product lifecycle.
• Customer Interaction: Interface directly with external customers to present verification status, review coverage results, address technical questions, and ensure verification deliverables meet product and customer requirements.

Qualifications

• Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 8-12+ years of experience in mixed-signal verification, AMS/DMS simulation, behavioral modeling, power management IC development, or related semiconductor design activities. Strong experience with switching regulators, battery chargers, PMICs, SystemVerilog, Verilog-AMS, UVM, Cadence Xcelium, Spectre, and mixed-signal verification sign-off methodologies is highly desirable. Experience developing behavioral models and debugging complex analog-digital interactions is a plus.
• Communication: Strong communication, teamwork, and customer-facing skills, with the ability to effectively collaborate across cross-functional engineering teams and present technical information to both internal and external stakeholders.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual‑use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.