Staff Mask Design Engineer

Socket.dev; Chandler (AZ); On-site; USD 150,000 - 230,000; Full time

Job summary

Socket.dev is seeking a Staff Mask Design Engineer to join its layout organization, focusing on analog and mixed-signal ICs for automotive applications, contributing to block and top-level layouts.

You will lead layout activities, collaborate with design, verification, CAD, and technology teams, apply advanced techniques, and ensure robust, manufacturable implementations that meet performance and quality targets.

Qualifications

• 8+ years of Analog and Mixed-Signal IC layout experience.
• Experience delivering layouts at IP, block, and Chip Top level.
• Automotive or safety-critical semiconductor experience is highly desirable.

Responsibilities

• Implement physical layouts for IP, block, and Chip Top level.
• Drive floorplanning for blocks and top-level designs.
• Define power supply strategy and signal distribution between blocks.
• Deliver analog/mixed-signal layout blocks and contribute to top-level floorplan strategy.
• Apply layout techniques for device matching, parasitic reduction, ESD protection, latch-up prevention, and yield.
• Execute DRC, LVS, ERC, DFM, and PEX verification.
• Follow Analog-on-Top and Mixed-Signal-on-Top workflows.
• Attend design reviews and report progress and risks.
• Collaborate with design, verification, CAD, and technology teams to minimize rework.
• Identify root causes and propose fixes after silicon/proto evaluation.
• Contribute to design-for-quality and reliability.
• Lead layout team activities and knowledge sharing.
• Participate in training and layout guideline documentation.

Skills

Floorplanning

Device matching

Parasitic management

Latch-up prevention

ESD protection

Top-level integration

Education

B.S./M.S. in Electrical/Electronics/Microelectronics

Tools

Cadence Virtuoso

Mentor Calibre

R3D

Job description

Job Summary:

We are looking for an experienced Staff Mask Design Engineer to join a highly skilled layout organization working on Analog and Mixed‑Signal ICs for Automotive applications.

The successful candidate will contribute at block and Chip top level, lead layout activities, collaborate closely with design and cross‑functional teams, and ensure robust physical implementation that meets performance, reliability, and quality requirements.

Job Purpose:

The purpose of this role is to deliver robust, high‑quality physical layouts for complex analog and mixed‑signal ICs, ensuring manufacturability, reliability, and on‑time delivery, while contributing to layout methodology, team capability, and continuous improvement.

Key Responsibilities:

• Implementing physical layouts for Automotive Business Line products at IP, block, and/or Chip Top level.


• Driving and delivering floorplanning activities for blocks and top‑level designs.


• Participating in power supply strategy definition and signal distribution between blocks.


• Delivering analog and mixed‑signal layout blocks and contributing to top‑level floorplan strategy.


• Applying state‑of‑the‑art layout techniques for device matching, parasitic reduction, ESD protection, latch‑up prevention, and yield optimization.


• Executing and signing off physical verification flows, including DRC, LVS, ERC, DFM, and parasitic extraction (PEX).


• Working according to Analog‑on‑Top and Mixed‑Signal‑on‑Top layout methodologies.


• Attending relevant project and design reviews, reporting progress, risks, and schedule impacts.


• Collaborating closely with design, verification, CAD, and technology teams to minimize rework and resolve physical implementation issues.


• Identifying root causes and proposing solutions for items observed during first silicon or prototype evaluation.


• Contributing to design‑for‑quality, ensuring layouts are verified, validated, and suitable for long‑term reliability and zero‑defect goals.


• Leading layout team activities, including task planning, execution, and knowledge sharing.


• Participating in and contributing to training activities, technical documentation, and layout guidelines.


• Taking a proactive role in personal development, continuous learning, and methodology improvement.


• Bachelor’s or Master’s degree in Electrical, Electronics, or Microelectronics Engineering.


• 8+ years of experience in Analog and Mixed‑Signal IC layout design.


• Proven experience delivering complex layouts at IP, block, and Chip Top level.


• Experience in automotive or safety‑critical semiconductor products is highly desirable.

Technical Skills:

• Strong expertise in analog layout techniques, including:
  
  
  
  • Floorplanning and top‑level integration
  
  
  • Device matching and symmetry
  
  
  • Parasitic management
  
  
  • Latch‑up prevention and ESD protection
  
  
  
  


• Solid understanding of electronics, semiconductor physics, and fabrication processes.


• Hands‑on expertise with layout and verification tools, including:
  
  
  
  • Cadence Virtuoso / Virtuoso XL (OA, PVS)
  
  
  • Mentor Graphics Calibre (DRC, LVS, PEX, DFM)
  
  
  • R3D and related parasitic extraction tools
  
  
  
  


• Experience with advanced CMOS BCD technologies


• Experience using Mixed‑Signal‑on‑Top (MSoT) flows


• Ability to define and execute advanced floorplan strategies

Soft Skills & Ways of Working:

• Strong team player, self‑motivated, and results‑oriented.


• Ability to work independently and collaboratively in a multisite, multicultural environment.


• Excellent verbal and written English communication skills.


• Clear, concise communication and presentation skills.


• Ability to propose innovative and pragmatic solutions.


• Strong focus on quality, reliability, and on‑time delivery.


• Willingness to undertake occasional international travel if required.


• Comfortable collaborating with cross‑functional teams including design, test, program management, and quality.

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier.

With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read ourDiversity & Inclusion Statement.

Renesas Electronics deals with dual‑use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.