Staff Application Engineer- Physical Design

Synopsys Inc; Sunnyvale (CA); On-site; USD 190,000 - 240,000; Full time

Benefits offered by this job

Health benefits

Financial benefits

Job summary

Synopsys Inc. is seeking an experienced ASIC physical design engineer to partner with customers on challenging 7nm+ designs. You will tackle RTL-to-GDS flows, timing closure, and PPA improvements using Fusion Compiler or ICC2 to move designs forward.

You will work directly with customers, translate constraints into concrete plans, run benchmarks, and contribute to methodology development while collaborating with R&D, product management, and field teams. Travel to customer sites may be required.

Qualifications

• Experience with RTL-to-GDS flows and advanced node challenges.
• Hands-on timing closure, placement, and routing on 7nm+ processes.
• Proficiency with Synopsys backend tools and static timing analysis.

Responsibilities

• Support customer engagements on Synopsys physical design tools to hit PPA targets.
• Debug complex physical design issues across RTL-to-GDS flow including timing and power.
• Develop and deliver methodology recommendations for customer constraints and schedules.
• Run benchmarks and proofs-of-concept to showcase AI-driven optimization.
• Collaborate with R&D, product management, and field teams to translate pain points into requirements.
• Present technical content to customer teams and management, linking tool capabilities to outcomes.
• Travel to customer sites for onsite support, training, and design reviews.

Skills

RTL-to-GDS flows

Placement

Clock tree synthesis

Routing

Timing closure

AI-driven optimization

Static timing analysis

Communication skills

Electromigration awareness

Education

Bachelor's degree in Electrical Engineering or equivalent

Master's degree (preferred)

Tools

Fusion Compiler

ICC2

Design Compiler

PrimeTime

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of physical design, where a bad placement decision at 5nm costs weeks and a routing congestion hotspot can kill a tapeout schedule. You know the difference between a flow that works on paper and one that actually closes timing at advanced nodes, and you have lived through enough iterations to spot the gap before it becomes a crisis. You are the engineer who gets called when a customer's design is stuck at 87% routing utilization or when their clock tree is burning 200mW more than it should, and you do not just debug the problem, you teach them how to think differently about their methodology.

Working directly with customers energizes you. You like the puzzle of understanding their constraints, their schedule pressure, their process quirks, and then translating that into a concrete plan using Fusion Compiler or ICC2 that actually moves their design forward. You do not need a perfect runbook to be effective. You ask the right questions, reproduce the issue, and work the problem until it is solved or until you have a clear path to escalation.

At Synopsys, you will be the technical bridge between our tools and the customers building the chips that power everything. The work is real, the problems are hard, and the impact is immediate.

What You'll Be Doing

• Support customer engagements on Synopsys physical design tools including Fusion Compiler, ICC2, and Design Compiler, helping them achieve PPA targets on advanced node designs
• Debug complex physical design issues across the RTL-to-GDS flow, including placement, CTS, routing, timing closure, and power optimization at 7nm, 5nm, and below
• Develop and deliver methodology recommendations tailored to customer design constraints, process technologies, and project schedules
• Run benchmarks and proof-of-concept flows to demonstrate tool capabilities, AI-driven optimization features, and advanced node methodologies
• Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature requests
• Present technical content to customer engineering teams and management, translating tool capabilities into business outcomes like reduced cycle time or improved yield
• Travel to customer sites as needed to provide onsite support, training, and design reviews

The Impact You Will Have

• Accelerate customer tapeout schedules by weeks through targeted methodology improvements and tool optimization strategies
• Enable successful adoption of Synopsys tools at key accounts, directly influencing design wins and renewals
• Shape product roadmaps by surfacing real-world customer challenges and advanced node requirements to engineering teams
• Build deep technical relationships with leading semiconductor companies, becoming their trusted advisor on physical design flows
• Reduce customer support escalations by proactively addressing methodology gaps and training engineering teams on best practices
• Contribute to the success of chips that will ship in millions of devices, from mobile processors to AI accelerators
• Help customers unlock the full value of their Synopsys investment, improving their ROI and competitive positioning

What You'll Need

• Bachelor's degree in Electrical Engineering or equivalent with 7+ years of hands-on ASIC physical design experience, or Master's degree with 5+ years
• Deep experience with RTL-to-GDS flows using industry-standard tools, including placement, optimization, clock tree synthesis, and routing
• Strong working knowledge of Synopsys backend tools, specifically Fusion Compiler or ICC2, with hands-on experience in timing closure, macro placement, and routing at advanced nodes
• Proficiency with static timing analysis tools, particularly PrimeTime , including setup/hold analysis and noise analysis
• Solid understanding of advanced node design challenges at 7nm and below, including FinFET effects, multi-patterning, and electromigration
• Experience with logical and physical synthesis flows and AI-driven methodologies for optimization
• Excellent communication skills with the ability to present technical concepts clearly to both engineering teams and management

Who You Are

• You can walk into a customer war room where timing is failing by 500ps at sign-off and quickly triage whether it is a methodology issue, a tool setting, or a fundamental design problem
• Comfortable context-switching between multiple customer engagements, you manage priorities without dropping threads or losing technical depth
• You explain complex tradeoffs like CTS topology choices or placement density targets in ways that make sense to a design lead who needs to make a decision today
• Customer-focused without being a pushover, you push back when a request does not align with best practices and offer a better path forward
• You document your work clearly enough that another engineer or the customer can pick up where you left off without a two-hour handoff call
• Energized by teaching, you genuinely enjoy the moment when a customer engineer understands why their flow was suboptimal and how to fix it going forward

The Team You'll Be Part Of

You will join the Customer Success Group, the team responsible for ensuring customers get maximum value from Synopsys physical design tools. This is a technical applications role working directly with semiconductor companies on their most challenging designs. You will collaborate closely with field sales, R&D engineering, and product management teams across Synopsys to deliver customer success and drive product adoption.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.