Sr. Staff/Principal PCIE Subsystem Architect

Qualcomm; San Diego (CA); On-site; USD 164,000 - 265,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a PCIe Subsystem Architect to define high-speed I/O architectures for next-gen AI datacenter products. You will drive subsystem architecture across accelerator cards and server-level deployments, collaborating with global teams.

The ideal candidate has deep PCIe/Ethernet expertise, familiarity with UCIe/CXL/NVMe, and a record of delivering scalable rack-level solutions. This role offers a challenging, international environment.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or related field with 10+ years of ASIC design/verification experience.
• Master's degree in Electrical Engineering, Computer Science, Computer Engineering with 8+ years of ASIC design/verification experience.
• PhD in Electrical Engineering, Computer Science, Computer Engineering with 6+ years of ASIC design/verification experience.
• 3+ years of experience with high-performance designs involving PCIe, Ethernet, or other high-speed I/O interfaces.

Responsibilities

• In-depth knowledge of PCIe, Ethernet, and other high-speed I/O interfaces used in datacenter and accelerator products.
• Strong understanding of PCIe ordering models, producer-consumer ordering, DMA flows, and high-speed serial interface behavior.
• Experience with PCIe error containment and recovery mechanisms such as AER, CRS, FLR, and reset separation.
• Experience with I/O virtualization and isolation technologies such as SR-IOV, SIOV, PF/VF isolation.
• Strong understanding of RAS, telemetry, reliability, and security requirements for server-class SoCs and accelerator subsystems.
• Good knowledge of scale-up and scale-out architectures, PCIe switch fabrics, and rack-level deployment considerations.
• Ability to work effectively in a high-caliber, international, multi-site engineering team.

Skills

PCIe expertise

CXL familiarity

UCIe familiarity

NVMe familiarity

High-speed I/O interfaces

Datacenter architectures

Education

Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field

Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field

PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field

Tools

PCIe PHY

Ethernet

Job description

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm is looking for an experienced PCIe Subsystem Architect to help define and deliver high-performance I/O architectures for next-generation AI products in the datacenter. The ideal candidate is a high-speed interfaces architect with deep expertise across PCIe, CXL, Universal Chiplet Interconnect Express (UCIe), Non-Volatile Memory Express (NVMe), Ethernet, and related datacenter connectivity standards. The selected candidate will define subsystem architecture and drive requirements from the accelerator card and server level through full-rack scale-up and scale-out deployments.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.

OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Responsibilities

• In-depth knowledge of PCIe, Ethernet, and other high-speed I/O interfaces used in datacenter and accelerator products.
• Strong understanding of PCIe ordering models, producer-consumer ordering, ARM ordering behavior, DMA flows, and high-speed serial interface behavior.
• Strong understanding of PCIe Gen6/Gen7 requirements, including FLIT mode, PAM4 signaling implications, link training, latency, error handling, and system-level tradeoffs.
• Experience with PCIe error containment and recovery mechanisms such as Advanced Error Reporting (AER), Downstream Port Containment (DPC), Configuration Request Retry Status (CRS), Function Level Reset (FLR), and reset separation.
• Experience with I/O virtualization and isolation technologies such as SR-IOV, SIOV, PF/VF isolation, and related software-visible requirements.
• Strong understanding of RAS, telemetry, reliability, and security requirements for server-class SoCs and accelerator subsystems.
• Good knowledge of scale-up and scale-out architectures, including PCIe switch fabrics, NIC connectivity, host-to-accelerator orchestration, and rack-level deployment considerations.
• Ability to work effectively in a high-caliber, international, multi-site engineering team.

Preferred Skills And Experience

• Good understanding of PCIe integrity, security, and confidential-compute features such as IDE, DOE/SPDM, TDISP, SR-IOV, and SIOV.
• Strong familiarity with PCIe CEM standards, add-in card deployment constraints, retimers, signal-integrity considerations, and system-level validation flows.
• Good understanding of emerging AI interconnect standards and ecosystems such as UCIe, UALink/UAL, and UEC.
• Good understanding of PCIe firmware, BIOS/UEFI, operating-system, driver, and system-software requirements.
• Good understanding of high-speed SerDes and PHY technologies, including PCIe PHY, Ethernet PHY, PAM4 signaling, and power/performance tradeoffs.
• Good knowledge of server SoC architectures with emphasis on security, RAS, virtualization, IOMMU/SMMU, DMA, address translation, and telemetry.
• Ability to engage with customers, product management, systems teams, and cross-functional architecture stakeholders to gather requirements and drive technical alignment.
• Excellent written and verbal communication skills, with the ability to create architecture specifications, requirement documents, and executive-level technical summaries.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field and 10+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• OR Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field and 8+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• OR PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related field and 6+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• 3+ years of experience with high-performance designs involving PCIe, Ethernet, or other high-speed I/O interfaces.

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Pay Range and Other Compensation & Benefits

$164,000.00 - $264,500.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.