Sr. Silicon Design Engineer: Hardware-Software Co-Design

Advanced Micro Devices, Inc.; Bellevue (WA); On-site; USD 150,000 - 260,000; Full time

Job summary

Advanced Micro Devices, Inc. (AMD) is seeking a Senior Silicon Design Engineer to co-design hardware-software interfaces for Instinct GPUs.

You will collaborate with hardware architects to model interactions between GPU microarchitecture, AI frameworks, and ROCm software, driving improvements in performance and energy efficiency across the AI compute stack. You will write and optimize GPU kernels, work across the Linux kernel DRM/GEM layer, ROCm runtime, IREE compiler, and AI frameworks like

Qualifications

• Industry experience at the boundary of GPU compute hardware and AI systems software.
• Strong computer architecture foundation: memory consistency and coherence models, GPU microarchitecture, pipelining.
• Proven performance modeling skills and analytical or simulation-based models.

Responsibilities

• Build performance and power models linking architectural decisions to workloads.
• Evaluate hardware features and API designs for AI training and inference targets.
• Write and optimize GPU kernels and compiler passes for microarchitectural characteristics.

Skills

CUDA/HIP

C/C++

Python

GPU architecture

Performance modeling

Linux kernel internals

IREE/ROCm

Education

Bachelor's or Master’s in CS/CE

Tools

LLVM/MLIR

IREE

ROCm stack

GPU profiling tools

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re redesigning next‑gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger— technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

The AMD AI Group is looking for a Senior Silicon Design Engineer to co‑design the hardware‑software interface for AMD Instinct™ GPUs. You will work with hardware architects to model and evaluate how GPU microarchitecture, AI frameworks, and the ROCm™ software stack interact, using that analysis to drive improvements in both performance and energy efficiency across the AI compute stack.

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top‑thinkers and engineers alike, ready to help elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

Your day‑to‑day: build performance and power models that connect architectural decisions to real workload behavior. Evaluate proposed hardware features and software API designs against AI training and inference targets. Write and optimize GPU kernels and compiler passes that exploit microarchitectural characteristics. Work across the stack: the Linux kernel DRM/GEM layer, the ROCm™ runtime, the IREE compiler, and AI frameworks and DSLs like PyTorch and Triton.

Hardware‑Software Co‑Design & Performance

• Leverage detailed performance models that bridge GPU microarchitecture and software execution, including instruction execution, memory hierarchy behavior, networking, and compute‑memory overlap. You will use those models to drive both software optimization and hardware design feedback.
• Analyze and characterize AI workloads (training and inference) against AMD Instinct™ microarchitecture to identify performance bottlenecks, inform silicon roadmap decisions, and validate that architectural features deliver expected real‑world speedups.
• Collaborate directly with AMD GPU hardware and firmware teams to evaluate proposed hardware features, providing software‑grounded analysis of how changes to the memory subsystem, cache coherence protocols, or execution units affect workloads that matter.
• Own the feedback loop between workload characterization and hardware design: build the methodology, tooling, and benchmarks that make this loop fast and evidence‑driven across Instinct generations.

Compiler & Runtime Infrastructure

• Contribute to the IREE compiler and ROCm™ stack, with focus on backend optimizations, runtime API extensions, and firmware command packet design that target AMD GPU microarchitecture.
• Design and optimize compute runtime paths including AI framework dispatch, data movement, and pipelining, minimizing overhead and maximizing hardware utilization for latency‑sensitive and throughput‑critical workloads.
• Work at the Linux kernel level on GPU compute infrastructure to improve asynchronous execution and reduce latency.

Cross‑Cutting

• Contribute to the open ROCm™ ecosystem, across the stack, in ways that raises the bar for the entire AMD AI developer experience.
• Develop reproducible benchmarks and performance regression infrastructure that keeps the full stack honest across compiler, runtime, and driver changes.
• Represent the software perspective in silicon architecture reviews and represent hardware realities to the software and framework teams. Be the person who holds both models in their head at once.
• Collaborate with AMD architecture teams to provide software feedback on next‑generation Instinct™ GPU designs for both training and inference workloads.

PREFERRED EXPERIENCE:

• Industry experience working at the boundary of GPU compute hardware and AI systems software.
• Strong computer architecture foundation: memory consistency and coherence models, GPU microarchitecture, pipelining, and the ability to reason precisely about what hardware is doing on a given workload.
• Demonstrated performance modeling skills and the ability to build analytical or simulation‑based models that predict real hardware behavior and use them to make engineering decisions.
• Proficiency in C and C++ in system‑level contexts, and Python for tooling, analysis, and framework‑level work.
• Experience with GPU programming via CUDA and/or HIP, including writing and optimizing compute kernels beyond library calls.
• Familiarity with Linux kernel internals relevant to GPU compute: DRM/GEM subsystem, kernel‑mode driver interfaces, memory management, and userspace‑kernel interaction patterns.
• Experience with compute runtimes and the full dispatch path from framework‑level operations to GPU execution.
• Experience with AI framework internals including PyTorch dispatcher, Triton compiler, or equivalent depth in how frameworks lower operations to hardware.
• Direct experience with AMD Instinct GPU architectures (MI300X, MI350X, MI355X) and the ROCm™ stack.
• Working knowledge of compiler infrastructure such as LLVM/MLIR‑based flows, backend code generation, or related optimization passes. Experience with IREE is a strong plus.
• Familiarity with modern AI model architecture: quantization techniques, KV cache, attention mechanisms and their variants, mixture‑of‑experts routing, or emerging state space models and an understanding of what these architectures demand from hardware.
• Experience with performance analysis tools for GPUs like profilers, trace viewers, hardware counters and building custom tooling on top of them.
• Publications or patents in HPC, ML systems, or GPU kernel optimization.

PREFERRED ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in Computer Science, Computer Engineering, or a related field.

LOCATION:

San Jose, CA

This role is not eligible for visa sponsorship.

AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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