Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning

Amazon Inc.; Austin (TX); On-site; USD 185,000 - 250,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

RSUs

Job summary

Annapurna Labs, an organization within Amazon, is seeking an ASIC Physical Design Methodology Engineer in Austin, TX to advance hardware design for ML accelerator chips. You will develop RTL2GDS flows, optimize CAD toolchains, and work with RTL, Physical, and Package teams to improve QoR and design reliability.

The role requires strong scripting abilities (Python/TCL) and extensive experience in ASIC, digital design, and post-silicon verification.

Qualifications

• 7+ years ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes.
• 7+ years of digital design in communication systems.
• 7+ years of full-custom analog or RF layout experience.
• Experience with post-silicon flow automation and verification.
• Bachelor's degree in Electrical Engineering or related field.

Responsibilities

• Define, develop and deploy physical design and verification methodologies for ML accelerator chips.
• Drive CAD flow optimizations for PPA and timing targets.
• Collaborate with RTL, Physical, and Package Design teams to improve flows.
• Create dashboards and reports for project tracking and QoR metrics.
• Interface with EDA vendors and troubleshoot tool flows independently.

Skills

ASIC implementation

Digital design

Python scripting

UVM

C programming

SystemC

RTL2GDS

Scripting (TCL)

CAD flow optimization

Education

Bachelor's degree in Electrical Engineering

Master's/PhD preferred

Tools

MATLAB

Python

C++

EDA tools

SystemC

Job description

Description

Annapurna Labs (our organization within Amazon Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

Amazon provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries.

Custom SoCs (System on Chip) live at the heart of Amazon Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.

Key job responsibilities

Define, develop and deploy innovative physical design and verification methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes

Drive Optimizations in CAD flows/methodologies for PPA and TAT improvements

Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability.

Fine tune cloud infrastructure to improve compute and storage utilization for physical design work.

Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies.

Be able to independently troubleshoot digital tool flow usage and deploy solutions;

Fluent in scripting languages such as TCL, Python, etc. and able to build scalable and efficient flows to support parallel design developments

Create Dashboard and Central reports for project tracking and visualizing QoR/stats

A day in the life

Basic Qualifications

• 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience

• 7+ years of digital design in communication systems experience

• 7+ years of full-custom analog or RF layout experience

• 7+ years of wireless communications systems and implementation experience

• 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience

• 7+ years of verification in communication systems experience

• 5+ years of UVM, C, System C, and scripting experience

• 3+ years of emulation experience

• Bachelor's degree in Electrical Engineering or a related field

• Knowledge of UVM and Matlab

• Knowledge of implementing chips with multiple power islands and power gating

• Knowledge of multiple access systems including OFDMA, TDMA, and CDMA

• Knowledge of end-to-end network system architecture from wireless physical layer to application endpoints

• Knowledge of serial protocols including SPI, I2C, I3C, and UART

• Knowledge of Python and Embedded C programming

• Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems or RF engineering

• Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards

• Experience leading or solely developing methodology and scripts for physical synthesis

• Experience taping out chips that have gone into high volume production

• Experience developing products for volume production

• Experience low power design techniques

• Experience delivering products to volume production

• Experience in modem L1/L2 algorithms development and architectures

• Experience in developing link and system level simulators using MATLAB, Python, or C+- Experience in test setup automation using MATLAB, Python, or Pearl

• Experience with Agile, TDD, BDD, CI, and Git

• Experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors

• Experience leading technical initiatives and key deliverables

• Experience with version control systems and CI/CD pipeline implementation

• Experience in Bare Metal Environment development, including linker scripts, page tables and NVIC

Preferred Qualifications

• Master's degree or Ph.D. degree in Electrical Engineering or related field

• Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs

• Experience with modern ASIC/FPGA design and verification tools

• Experience with SOC bring-up and post-silicon validation

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits .

USA, TX, Austin - 185,200.00 - 250,000.00 USD annually