Sr. Engineer, Performance Infrastructure

Tenstorrent; California (MO); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a talented engineer to join the CPU design team, driving infrastructure for performance analysis, correlation, and verification. You will work on a RISC-V based CPU, collaborating with core architects and RTL teams to deliver a highly efficient design.

The role is hybrid, located in Austin, TX or Santa Clara, CA, with opportunities across experience levels. Strong candidates will have expertise in C++ and Python, experience with verification and high-performance CPU

Qualifications

• Proficient in C++ and Python with experience using industry-standard tools.
• Experience with verification infrastructure and CPU architecture concepts.
• Proven ability to debug RTL and logic across design hierarchies.

Responsibilities

• Drive CPU microarchitecture improvements and verify RTL against performance models.
• Enhance the design environment and development workflows for efficiency.
• Own the performance correlation framework, including tracking and visualization tools.
• Collaborate with RTL engineers and core architects to hit performance targets.

Skills

C++

Python

Performance analysis

Verification

RTL debugging

Tools

Simulation tools

Emulation tools

Open-source tools

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a talented engineer to join our CPU design team to drive infrastructure for performance analysis, correlation and verification. You’ll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Strong problem solver who can identify complex issues, develop practical solutions, and drive them through implementation.


• Enjoy building tools and improving the infrastructure, workflows, and methodologies that make CPU development more efficient.


• Skilled in C++ and Python, with experience using industry-standard compilation, simulation, and emulation tools.


• Experience with verification infrastructure and methodologies along with knowledge of high-performance CPU architecture and microarchitecture.


• Proficient in debugging RTL and logic across multiple design hierarchies and pre-silicon environments.

What We Need

• Join a team driving improvements in CPU microarchitecture, verifying performance, and correlating results between RTL and the performance model.


• Enhance the design environment, tools, and methodologies to improve development efficiency.


• Own the performance correlation framework, including tracking, visualization, and analysis tools.


• Collaborate closely with RTL engineers and core architects to meet performance goals, debug miscorrelation, and verify performance features.


• Use innovative techniques to optimize power, performance, and area while driving performance experiments and evaluating results.

What You Will Learn

• End-to-end exposure to CPU design from microarchitecture through performance convergence and validation.


• Hands-on experience with performance models, correlation, and analysis across pre-silicon and post-silicon phases.


• Experience integrating open-source and industry-standard tools to improve design flows and results.


• How to work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.