Sr. Director Hardware Development

Advanced Micro Devices, Inc.; Santa Clara (CA); Hybrid; USD 220,000 - 360,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Advanced Micro Devices, Inc. is seeking a Senior Director of Hardware Development to lead next-generation scale-up switch system design within the Networking Technology Solutions Group.

You will oversee end-to-end hardware development, defining system architecture and roadmaps to support AI infrastructure goals. The ideal leader has a proven record delivering complex high-speed hardware from concept through production and will guide global teams across electrical, mechanical, thermal, and SI/PI

Qualifications

• Bachelor's degree in electrical engineering, Computer Engineering, or a related field.
• Master's degree or higher preferred.
• Experience leading high-performance networking systems or AI infrastructure platforms.

Responsibilities

• Define and drive system architecture for scale-up switch platforms (800G/1.6T+).
• Establish hardware roadmap, design strategy and technical direction.
• Lead end-to-end hardware development: architecture, schematic, PCB, bring-up, validation, production readiness.
• Oversee high-speed interconnect design (PCIe Gen6/Gen7, 200G+ Ethernet).
• Build and mentor global teams across electrical, SI/PI, mechanical, and thermal engineering.

Skills

Scale-up switch systems

High-speed hardware

PCIe Gen6/Gen7

System architecture

Team leadership

FPGA/ASIC integration

Board and system bring-up

Education

Bachelor's in electrical/computer engineering

Master's degree preferred

Tools

Cadence

Altium

Simulation tools

Scripting

Job description

THE ROLE

This is an exciting opportunity for an experienced Senior Director of Hardware Development to lead next-generation scale-up switch system design within AMD's Networking Technology Solutions Group (NTSG). This leader will drive end-to-end hardware architecture, development, and deployment for high-performance AI networking platforms, with responsibility for delivering complex, high-speed systems that support AMD's AI infrastructure roadmap.

The Person

The ideal candidate is a seasoned engineering leader with a proven track record of delivering complex, high-speed hardware systems from concept through production. This individual brings deep technical judgment, strong execution discipline, and the ability to lead multidisciplinary teams across electrical, SI/PI, mechanical, and thermal engineering. They will shape technical strategy, scale team capabilities, and partner effectively across global engineering, manufacturing, customer, and executive stakeholder groups.

Key Responsibilities

• Define and drive system architecture for scale-up switch platforms, including 800G/1.6T+ class systems.
• Establish the hardware roadmap, design strategy, and technical direction aligned with AMD's AI infrastructure goals.
• Serve as the senior technical authority across board, system, and interconnect design.
• Lead end-to-end hardware development, including architecture, schematic design, PCB layout, bring-up, validation, and production readiness.
• Drive high-speed interconnect design across PCIe Gen6/Gen7, UAL/XGMI, 200G+ Ethernet, and related technologies with strong SI/PI rigor.
• Oversee system-level validation, electrical bring-up, compliance, debug, root-cause analysis, and corrective actions for switch and NIC platforms.
• Build, mentor, and lead high-performing global teams across electrical, SI/PI, mechanical, and thermal engineering disciplines.
• Manage headcount planning, capability development, vendor partnerships, and global development execution.
• Partner closely with ASIC, packaging, optics, platform architecture, system software, manufacturing, quality, field, product management, customer, and hyperscale teams.
• Communicate technical direction, risks, trade-offs, and execution status to executive leadership.
• Drive cost optimization, second-source strategy, design-for-manufacturability improvements, and innovation in validation methodology and AI-enabled engineering workflows.

Preferred Experience

• Extensive experience leading high-performance networking systems, scale-up switch platforms, or AI system architectures.
• Deep expertise in PCIe Gen6/Gen7, UAL/XGMI, DDR5/DDR6, 200G+ Ethernet, and high-speed interconnect technologies.
• Strong background in system-level SI/PI design, validation, debug, and root-cause analysis.
• Hands-on experience with complex board and system bring-up, PCB design, high-speed layout, and system integration.
• Experience with hardware development tools such as Cadence, Altium, simulation environments, and scripting.
• Proven success leading cross-functional and globally distributed engineering teams.
• Experience with FPGA, CPLD, or ASIC integration is preferred.
• Background in optical interconnects and scale-out/scale-up system architecture is preferred.
• Familiarity with configuration management tools such as Git or SVN is preferred.

Academic Credentials

• Bachelor's degree in electrical engineering, Computer Engineering, or a related field required.
• Master's degree or higher preferred.

This role is not eligible for visa sponsorship.

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Benefits and Policies

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.