Sr. ASIC DFT Engineer (Silicon)

SPACE EXPLORATION TECHNOLOGIES CORP; Irvine (CA); On-site; USD 125,000 - 150,000; Full time

Benefits offered by this job

Employee Stock Purchase Plan

Medical, vision, and dental coverage

401(k) retirement plan

3 weeks of paid vacation

Paid parental leave

Job summary

SPACE EXPLORATION TECHNOLOGIES CORP in California, Irvine, is hiring for a DFT Engineer. The role involves optimizing DFT architectures, integrating DFT IPs, and running ATPG tools to ensure effective testing of semiconductor designs.

Qualified candidates should possess a Bachelor's in electrical engineering or related fields, combined with significant experience in the semiconductor industry. The position comes with competitive compensation and comprehensive benefits.

Qualifications

• 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing.
• Master’s or PhD in electrical engineering, computer engineering, physics, or related engineering field preferred.
• Extensive experience in post-silicon bring-up, silicon debug, and yield optimization.

Responsibilities

• Implement and optimize DFT architectures, including scan insertion and logic BIST.
• Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems.
• Set up and run Automatic Test Pattern Generation (ATPG) tools.

Skills

Semiconductor Design For Test (DFT)

Post-silicon validation

Production testing

Programming (Perl, Python, Tcl, C++)

Problem-solving skills

Communication skills

Education

Bachelor’s degree in electrical engineering, computer engineering, or physics

Tools

Siemens Tessent tools

Automated Test Equipment (ATE)

Job description

SpaceX is actively developing the technologies to make human life on Mars possible and is deploying Starlink, the world’s most advanced broadband internet system.

RESPONSIBILITIES

• Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
• Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
• Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, generating patterns for stuck‑at, transition, and path‑delay fault models with a focus on pattern compression, diagnosis, and hierarchical test flows
• Run and debug non‑timing and SDF annotated gate‑level simulations
• Create and validate DFT patterns for post‑silicon bring‑up and assist with ATE debug throughout silicon characterization cycles
• Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C++

BASIC QUALIFICATIONS

• Bachelor’s degree in electrical engineering, computer engineering, or physics
• 5+ years of experience in semiconductor Design For Test (DFT) engineering, post‑silicon validation, and/or production testing

PREFERRED SKILLS AND EXPERIENCE

• Master’s or PhD in electrical engineering, computer engineering, physics, or related engineering field
• Extensive experience in post‑silicon bring‑up, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs
• Hands‑on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high‑volume manufacturing test development and debug
• Experience collaborating with cross‑functional teams (design, verification, manufacturing) to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows
• Knowledge of industry standards for testability (e.g., IEEE 1500, 1687) and experience with low‑power DFT techniques using Siemens Tessent
• Experience with In‑System Test (IST), boundary scan (IEEE 1149.1), functional testing in embedded systems, or board‑level diagnostics, preferably using Siemens Tessent tools
• Hands‑on experience with Tessent Streaming Scan Network
• Experience with cell‑aware fault models in ATPG
• Excellent problem‑solving skills with the ability to analyze complex test failures and implement corrective actions
• Strong communication skills for documenting test strategies, reporting results, and presenting to stakeholders
• Ability to work in a fast‑paced environment, handling multiple projects and adapting to evolving technology nodes (e.g., 7nm and below)

ADDITIONAL REQUIREMENTS

• Ability to work extended hours and weekends as needed to meet critical milestones

COMPENSATION AND BENEFITS

Pay Range:

• Level 1: $125,000 - $150,000
• Level 2: $145,000 - $175,000

Eligibility: U.S. citizen, lawful permanent resident, or eligible for ITAR authorizations.

• Long‑term incentives, including company stock or cash awards and potential discretionary bonuses
• Employee Stock Purchase Plan allowing discounted purchase of additional stock
• Medical, vision, and dental coverage
• 401(k) retirement plan
• Short‑term and long‑term disability insurance
• Life insurance
• Paid parental leave
• Discounts and perks
• 3 weeks of paid vacation
• 10+ paid holidays per year
• Paid sick leave in accordance with company policy

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.