Sr. ASIC Design Engineer (Silicon Engineering)

Spacex; Austin, Northern (TX, KY); Hybrid; USD 150,000 - 190,000; Full time

Job summary

SpaceX in Austin, TX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop next‑generation ASICs for Starlink and space infrastructure.

You will define micro-architecture, write RTL in Verilog/SystemVerilog, and work with verification, timing, and physical teams to deliver fully verified designs on schedule, facing challenging clock domains and power optimization. This role requires strong collaboration and hands-on debugging, with extended hours for mission-critical deadlines.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of RTL implementation experience.
• Willingness to work extended hours for mission-critical deadlines.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements and system limitations.
• Define micro-architecture, implement RTL in Verilog/SystemVerilog, integrate top level and deliver fully verified, synthesis/timing-clean design.
• Work with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraints for IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation.

Skills

Clock domain crossings

Embedded CPU subsystems

AXI/AHB protocols

High speed design

HDL tools

Education

Bachelor’s degree in EE/CE/CS

Tools

HDL simulators

HDL Lint tools

EDA tools

Synthesis/timing tools

Job description

Austin, TX

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal ofenabling human life on Mars.

SR. RTL DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting‑edge next‑generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

• Evaluate architectural trade‑offs based on features, performance requirements and system limitations
• Define micro‑architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
• Work closely with verification team to ensure all aspects of the design are covered and verified
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
• Participate in silicon bring‑up and validation

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

• Ability to solve complex problems including clock domain crossings and power optimization
• Experience with embedded CPU subsystems
• Experience with standard bus protocols (e.g. AXI, AHB, etc.)
• Experience with high speed and low power design techniques
• Experience with EDA tools such as HDL simulators and HDL Lint tools
• Team-player, can‑do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours or weekends as needed for mission critical deadlines
• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here .

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

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