Sr. Analog/Mixed Signal Design Engineer

AMD; Austin (TX); Hybrid; USD 140,000 - 200,000; Full time

Job summary

AMD in Austin, TX is seeking a Senior Engineer to lead LDO design for next‑generation SoCs. You will own end‑to‑end development from concept to silicon bring‑up, collaborating with architects, analog/mixed‑signal designers, and validation teams.

The ideal candidate brings deep analog design expertise, hands‑on schematic work, and familiarity with FinFET processes. This hybrid role requires strong leadership and problem‑solving across teams.

Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, or related discipline.
• Expertise in analog LDO architecture and system operation.
• Experience with silicon bring‑ups and validation.
• Strong communication and cross‑functional collaboration.
• Familiarity with FinFET devices and process‑driven design.

Responsibilities

• Lead feasibility, design, and integration of high‑performance LDOs for AMD SoCs.
• Develop behavioral models for system analysis and power integrity simulations.
• Drive silicon bring‑ups, debugging, validation, and performance optimization.
• Contribute to AMD analog design methodologies.
• Collaborate with cross‑functional teams for robust architecture and integration.
• Perform hands‑on schematic design, silicon evaluation, and debugging as needed.

Skills

Analog LDO architecture

System integration

Hands-on schematic design

AI‑assisted design

Cross‑functional leadership

Lab debugging

Education

MS or PhD in Electrical/Computer Engineering

Tools

EDA tools

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE

Join a high‑impact engineering team shaping the power‑delivery architecture for next‑generation AMD SoCs. As a Senior Engineer, you will lead the design and validation of advanced Linear Voltage Regulators (LDOs) that enable industry‑leading performance and power efficiency. This role offers the opportunity to own designs end‑to‑end — from concept feasibility and modeling through silicon bring‑up and production.

You’ll collaborate closely with world‑class architects, analog/mixed‑signal designers, methodology experts, and validation teams. Along the way, you’ll deepen your expertise across FinFET technologies, system‑level power integration, and AI‑driven design methodologies. This is an environment where innovation, technical leadership, and hands‑on problem solving are not just encouraged — they’re essential.

THE PERSON

The ideal candidate is a technically curious and solutions‑oriented engineer who thrives in complex power‑delivery environments and enjoys taking ownership from concept through silicon. They are effective communicators who can lead cross‑functional discussions, influence architectural decisions, and collaborate seamlessly with design, methodology, and validation teams. This person is equally comfortable diving into hands‑on design work, modeling, and lab debug, and they bring a strong foundation in analog/mixed‑signal principles, FinFET device behavior, and system‑level integration. They leverage AI‑based tools to accelerate design workflows, adapt quickly to evolving product requirements, and bring a structured, program‑minded approach that ensures alignment and execution across teams.

KEY RESPONSIBILITIES

• Lead feasibility, design, and system integration of high‑performance LDOs for AMD SoCs
• Develop and refine behavioral models to support system‑level analysis and power‑integrity simulations
• Drive silicon bring‑ups, debug, validation, and performance optimization
• Contribute to and improve AMD analog design methodologies
• Collaborate closely with cross‑functional teams to ensure robust architecture, implementation, and integration
• Perform hands‑on schematic design, silicon evaluation, and debugging as needed

PREFERRED EXPERIENCE

• Expertise in analog LDO architecture, design, and system operation
• Strong communication, leadership, and cross‑functional program‑management capabilities
• Hands‑on experience with silicon bring‑ups, validation, and debug
• Background in analog/mixed‑signal circuit fundamentals and layout‑dependent effects
• Proficiency with industry‑standard schematic/layout tools
• Familiarity with FinFET device behavior and process‑driven design considerations
• Experience completing full design cycles from concept to productionAbility to leverage AI tools or agents to accelerate modeling, design, and validation

ACADEMIC CREDENTIALS

• MS or PhD in Electrical Engineering, Computer Engineering, or a related discipline

LOCATION:

• Austin, TX

This role is not eligible for visa sponsorship.

#LI-DP1

#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.