Sr AI Driver Architect - Neuromorphic Computing

Intel Corporation; Santa Clara (CA); On-site; USD 202,000 - 285,000; Full time

Job summary

Intel Corporation is seeking a seasoned engineer to lead the neuromorphic driver and firmware stack, from pre-silicon modeling through production release. You will shape the technical vision, drive architecture, and work hands-on across device drivers, firmware, and interfaces with hardware teams.

You will mentor engineers, collaborate with runtime, validation, and customers, and ensure security and reliability of the platform in edge/robotic contexts.

Qualifications

• BSc, MSc, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.

Responsibilities

• Define and drive the technical vision, architecture, and roadmap for Intel's neuromorphic driver and firmware stack, while contributing hands-on to design and implementation.
• Architect, develop, and optimize the driver and firmware components that operate the device, including memory mapping, interrupts, and power management.
• Partner with hardware architects to define hardware/software interfaces for future silicon and drive software bring-up from pre-silicon to post-silicon tuning.
• Own production readiness including security, reliability, diagnosability, serviceability, and field support.
• Collaborate with runtime, compiler, application, and validation teams, and with customers to translate requirements into robust software capabilities.
• Provide technical leadership, establish engineering practices, and mentor engineers.

Skills

C/C++

Python

Driver architecture

Firmware

Pre-silicon bring-up

Mentoring

Cross-functional leadership

Software verification

Performance profiling

Education

BSc / MSc / PhD in CS/CE/EE or related field

Tools

Simics

FPGA

Linux kernel / RTOS

CI/CD tooling

Job description

Position Overview

Join the team building Intel's product-grade neuromorphic AI execution stack targeting edge and robotic systems. In this role, you will architect and lead the development of the device drivers and firmware, working closely with hardware, runtime, and validation teams to deliver a robust and efficient foundation for devices attached to a host or running standalone. You will own this layer from pre-silicon definition through production release while remaining hands-on in architecture and implementation.

Responsibilities

• Define and drive the technical vision, architecture, and roadmap for Intel's neuromorphic driver and firmware stack, while contributing hands-on to critical design and implementation.
• Architect, develop, and optimize the driver and firmware components that operate the device, covering command submission and execution control, memory mapping and data movement, interrupts, power management, and reset and recovery, whether the device is attached to a host or runs standalone.
• Partner with hardware architects to define the hardware/software interface of future silicon and drive software bring-up from pre-silicon modeling and emulation through post-silicon power-on and tuning.
• Own the production readiness of this layer, including security, reliability, diagnosability, and serviceability, along with the validation needed to release it and support it in the field.
• Collaborate with runtime, compiler, application, and validation teams, as well as customers and external partners, to translate platform and workload requirements into robust software capabilities.
• Provide technical leadership across the driver and firmware area by establishing engineering practices and mentoring engineers.

About the Organization

As part of Intel's CTO Office, you will join a vertically integrated incubation effort dedicated to bringing Intel's neuromorphic technology innovations to market. Our diverse team of engineers and researchers has pioneered sparse, event-based, neuromorphic architecture over multiple generations and is now focused on commercializing the technology in future Intel and partner products.

Minimum qualifications

• BSc, MSc, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.
• 5+ years of experience developing and shipping production device drivers and device firmware, or comparable low-level systems software, for accelerators, GPUs, or other complex hardware devices, including the interfaces between them.
• 5+ years of experience leading the architecture and design of driver or firmware subsystems for complex hardware platforms, including defining technical direction and guiding implementation.
• 5+ years of experience defining hardware/software interfaces together with hardware architects, and leading software bring-up from pre-silicon development on virtual platforms, simulators such as Simics, emulation, or FPGA, through post-silicon power-on, validation, and tuning.
• 5+ years of experience designing driver or firmware subsystems for production readiness, covering security, reliability, recovery, and the tracing, telemetry, and diagnostics needed to debug across hardware, firmware, driver, operating system, and runtime boundaries and to support a product in the field.
• 5+ years of experience mentoring engineers and leading delivery across cross-functional teams spanning hardware, firmware, systems software, and validation.
• 10+ years of hands-on experience developing maintainable, production-grade systems software in C/C++, with proficiency in Python for tooling, automation, and validation, using disciplined engineering practices such as design and code reviews, profiling, benchmarking, regression testing, build/toolchain management, and CI/CD.
• 1+ years of hands-on experience with agentic software engineering, routinely using AI agents to design, implement, test, and review production code.

Preferred qualifications

• Experience with Linux device driver development, embedded or real-time Linux, or RTOS-based firmware, including upstream contribution or formal driver qualification and certification for production platforms.
• Experience integrating drivers and firmware with accelerator runtimes and programming models such as oneAPI Level Zero, OpenVINO, CUDA, SYCL, or OpenCL.
• Experience with platform security, including secure boot, firmware signing and attestation, and firmware update and recovery flows.
• Experience bringing up and scaling multi-chip accelerator systems, including device-to-device interconnects and both PCIe-attached and SoC-integrated form factors.
• Experience with parallel computing paradigms or spatial, dataflow, event-driven, or other unconventional AI hardware accelerators.
• Experience in HW/SW co-design, hardware simulator or emulation model development, or performance modeling.
• Experience delivering embedded or edge accelerator platforms under real-time, reliability, or power constraints, including robotics software ecosystems such as ROS 2.
• Prior contributions to open-source software projects.

Job Type

Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Oregon, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Annual Salary Range

Annual Salary Range for jobs which could be performed in the US: $201,580.00-284,580.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.