SoC Hardware Architect

Ericsson GmbH; Austin (TX); On-site; USD 200,000 - 280,000; Full time

Job summary

Ericsson in Austin, Texas seeks a Principal SoC Hardware Architect to own the binding between AI workloads and custom silicon. This role requires deep expertise in AI inference, memory hierarchies, and hardware–software co-design to ensure feasibility before tape-out.

You will bridge model engineering, AI infrastructure, and silicon teams so every major hardware investment is architecturally sound and software-accessible, guiding compute investments and architecture choices.

Qualifications

• 12+ years of industry experience across AI, systems, or silicon.
• Experience at the intersection of hardware and intelligent compute systems.
• Hardware/software co-design leadership across full product cycles.
• Demonstrated performance modeling expertise — analytical, simulation, or cycle-approximate.
• Track record of influencing architectural and product decisions across multiple technical organizations.
• Exceptional written communication and technical specification ability.
• Strong Python and C++ skills.

Responsibilities

• Analyze workload specific testcases tailored to real-world applications and translate them into concrete hardware requirements.
• You connect model engineering, AI infrastructure, and silicon architecture teams so major hardware investments are architecturally sound and software-accessible.
• When workload ambition outpaces hardware capability, you find the path forward.
• When silicon innovation creates a performance unlock, you ensure the software stack can reach it.

Skills

Python

C++

Job description

Grow with us

SoC Hardware Architect

The Architect Who Closes the Gap. The Engineer Who Makes Silicon Inevitable.

Location: Austin, TX Team: Cross-functional leadership across Model Engineering, AI Infrastructure, and Silicon Architecture

The Problem Nobody Else Is Solving

Most chip programs are full of brilliant people who never quite speak the same language.

Researchers build ambitious AI models. Silicon teams build powerful hardware. Infrastructure teams wire it all together. And somewhere in the space between those three worlds — in the handoffs, the assumption gaps, the untranslated requirements — massive performance dies quietly on the floor.

We're not hiring someone to manage that problem. We're hiring the person who architects it out of existence.

The Role

As Principal SoC Hardware Architect, you will own the most consequential technical contract in the company: the binding agreement between what AI workloads demand, what software systems can express, and what custom silicon can physically deliver.

This is not a support role. This is not a liaison role. This is the highest-leverage engineering seat in the building — the person who looks at a next-generation LLM, a multimodal inference pipeline, or a signal processing workload and answers the question that determines whether a chip program succeeds or settles:

\"Here's exactly what this workload needs from silicon — and here's the proof it will work before we ever tape out.\"

Your decisions won't live in documents. They'll be etched into hardware. Your performance models will guide compute investments. Your architectural direction will shape memory hierarchies. Your cross-team alignment will determine whether the company builds capable hardware — or hardware nobody else can touch.

What You'll Own

Analyze workload specific testcases tailored to real-world applications, using LLMs, multimodal systems, signal processing pipelines, inference engines - and translate them into the concrete hardware requirements that can be implemented.

You are the bridge that doesn't bend. You connect model engineering, AI infrastructure, and silicon architecture teams so that every major hardware investment is both architecturally sound and software-accessible. When workload ambition outpaces hardware capability, you find the path forward. When silicon innovation creates a performance unlock, you make sure the software stack can actually reach it.

Performance Modeling Ownership

Before a single gate is placed, your analytical, simulation, and cycle-approximate performance models are already shaping the architecture. You build and create the performance modeling environment that determine compute investments, memory hierarchy decisions, and feature prioritization — turning uncertainty into defensible, data-driven direction.

Real Workload Validation

You profile real workloads on real and future platforms. You find the bottlenecks — in memory, compute, scheduling, and architecture — and you feed those findings directly into the next hardware and software cycle. No guesswork. No assumptions. Just ground truth.

Strategic Technical Translation

You align people who think in different languages. Hardware architects, AI researchers, and infrastructure teams all operate with different mental models and different vocabularies. You translate across all of them — grounding every product decision in real workloads, measurable constraints, and practical execution paths.

Join our Team

What You Bring

AI/ML Systems Depth You understand modern AI architectures from the inside — inference systems, quantization strategies, deployment constraints, and how workload behavior actually manifests in silicon utilization. You don't just know what a Transformer does. You know what it costs.

Silicon Architecture Fluency

You've worked with processor, accelerator, or custom silicon architectures. Compute pipelines, memory hierarchies, on-chip interconnects, performance tradeoff analysis — this is native territory for you, not background reading.

Required Qualifications

• 12+ years of industry experience across AI, systems, or silicon
• Proven experience at the intersection of hardware and intelligent compute systems
• Hardware/software co-design leadership across full product cycles
• Demonstrated performance modeling expertise — analytical, simulation, or cycle-approximate
• Track record of influencing architectural and product decisions across multiple technical organizations
• Exceptional written communication and technical specification ability
• Strong Python and C++ skills

Strongly Preferred

• Experience with custom silicon, accelerators, or advanced hardware platforms
• Prior involvement in ISA definition, memory hierarchy design, or accelerator roadmap decisions

Why This Seat Matters

Capable hardware gets built every year. Truly differentiated hardware — silicon that was purpose-built for the workloads that define an industry — is extraordinarily rare.

The difference between those two outcomes is usually one person: the architect who understood the workload deeply enough, the silicon clearly enough, and the software stack completely enough to hold the whole picture together.

That's the person we're building this role for.

Ericsson uses a merit-based hiring approach that values people with different experiences, perspectives and skillsets. We truly believe this approach drives innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity employer, learn more.

If you need assistance or to request an accommodation due to a disability, please contact Ericsson at [e-mail].

DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.

Primary country and city: USA || Austin, Texas

Job details: Developer

Compensation and Benefits at Ericsson

At Ericsson, we know that our people are the key to our success. We offer a competitive package to help with your individual needs and goals.

Your Pay

The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job-related knowledge, qualifications, skills, education, training, and experience.

• LOCATION: Austin, Texas

Your Health

Ericsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents.

Your Financial Security

We invest in both your short and long-term financial wellbeing. The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson’s full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits. Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short-term and long-term disability coverage. Employees also have the option to participate in Ericsson’s Stock Purchase Plan.

Your Time

Your work-life balance is important to us. New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro-rated based on the employee’s start date. Furthermore, Ericsson provides up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.

Additional Benefits

Ericsson offers many other company-paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.