SoC Design Verification Engineer

UST; Mountain View (CA); On-site; USD 101,000 - 152,000; Full time

Benefits offered by this job

Paid vacation and sick leave

Paid holidays

401(k) Retirement Plan with employer 


Health insurance (medical, dental, and

Job summary

UST is seeking two experienced SoC Design Verification Engineers to own functional and performance verification for complex System-on-Chip designs in Mountain View, CA. You will build UVM-based verification environments, develop test benches, and create coverage models that drive quality before silicon.

Collaboration with design and architecture teams is essential. Ideal candidates have 3–5 years of SoC verification, strong SystemVerilog/UVM skills, and proficiency in Python/C++.

Qualifications

• 3-5 years of SoC verification experience, including SoC-level functional and performance verification.
• Bachelor's or master's degree in electrical engineering, computer engineering, or a related field.
• Strong understanding of digital design principles and SoC architecture.
• Proficiency in SystemVerilog and UVM for building verification environments.
• Proficiency in Python and C/C++ for scripting and test development.
• Hands-on experience with simulation tools such as Synopsys VCS or Cadence Xcelium, including debugging simulation results.

Responsibilities

• Develop and execute verification plans for complex SoC designs, covering functional and performance verification at the core and SoC levels.
• Perform functional and performance verification using simulation, emulation, and formal verification techniques.
• Create and maintain UVM-based verification environments, test benches, test cases, and coverage models in SystemVerilog and C++.
• Run regressions in Synopsys VCS or Cadence Xcelium, and debug and analyze simulation results to isolate and resolve design issues.
• Review design specifications and architecture with design teams to identify verification challenges early in the development cycle.
• Develop Python and C/C++ scripts to automate verification flows and results analysis.
• Document verification results, track coverage and progress, and participate in code reviews to improve verification methodologies.

Skills

C

C++

SystemVerilog

UVM

SoC Architecture

Emulation

AHB

AXI

Cadence Xcelium

Coverage Modeling

DDR

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree in Electrical Engineering or Computer Engineering

Tools

Cadence Xcelium

Job description

SoC Design Verification Engineer

The Role

UST is searching for two experienced SoC Design Verification Engineers to own functional and performance verification for complex System-on-Chip designs. You will build and maintain UVM-based verification environments, and develop test benches, test cases, and coverage models that take a design from core-level verification through full SoC integration. You will work closely with design and architecture teams to clarify specifications, surface verification risks early, and protect the quality and reliability of our products. Success in this role means closing coverage against the verification plan and catching design defects before silicon is committed.

What You'll Do

• Develop and execute verification plans for complex SoC designs, covering functional and performance verification at the core and SoC levels.
• Perform functional and performance verification using simulation, emulation, and formal verification techniques.
• Create and maintain UVM-based verification environments, test benches, test cases, and coverage models in SystemVerilog and C++.
• Run regressions in Synopsys VCS or Cadence Xcelium, and debug and analyze simulation results to isolate and resolve design issues.
• Review design specifications and architecture with design teams to identify verification challenges early in the development cycle.
• Develop Python and C/C++ scripts to automate verification flows and results analysis.
• Document verification results, track coverage and progress, and participate in code reviews to improve verification methodologies.

This position description identifies the responsibilities and tasks typically associated with the performance of the position. Other relevant essential functions may be required.

What You Need

Required

• 3-5 years of SoC verification experience, including SoC-level functional and performance verification
• Bachelor's or master's degree in electrical engineering, computer engineering, or a related field
• Strong understanding of digital design principles and SoC architecture
• Proficiency in SystemVerilog and UVM for building verification environments
• Proficiency in Python and C/C++ for scripting and test development
• Hands‑on experience with simulation tools such as Synopsys VCS or Cadence Xcelium, including debugging simulation results

Preferred

• Proficiency in Verilog or VHDL
• Experience with formal verification techniques
• Experience with emulation platforms
• Experience with OVM or VMM verification methodologies
• Working knowledge of industry-standard protocols such as AXI, AHB, PCIe, and DDR

Location & Compensation

Compensation can differ depending on factors including but not limited to the specific office location, role, skill set, education, and level of experience. UST provides a reasonable range of compensation for roles that may be hired in various U.S. markets as set forth below.

Role Location: Mountain View, CA

Compensation Range: $101,000 - $152,000

Who We Are

Since 1999, UST has worked side by side with the world's best companies to make a powerful impact through transformation. Headquartered in the United States, UST is powered by technology, driven by AI, inspired by people, and led by our purpose, we partner with our clients from design to operation. Our AI-driven digital solutions, proprietary platforms, engineering, R&D, products, and innovation ecosystem turn core challenges into impactful, disruptive business outcomes. With deep industry knowledge and a future‑ready mindset, we infuse expertise, innovation, and agility into our clients' organizations-delivering measurable value and positive lasting change for them, their customers, and communities around the world. Together, with 30,000+ employees in 30+ countries, we build for boundless impact-touching billions of lives in the process. Visit us at .

Benefits

• Full-time, regular employees accrue a minimum of 10 days of paid vacation per year, receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year), 10 paid holidays, and are eligible for paid bereavement leave and jury duty.
• They are eligible to participate in the Company's 401(k) Retirement Plan with employer matching.
• They and their dependents residing in the US are eligible for medical, dental, and vision insurance, as well as the following Company-paid Employee Only benefits: basic life insurance, accidental death and disability insurance, and short- and long-term disability benefits.
• Regular employees may purchase additional voluntary short-term disability benefits, and participate in a Health Savings Account (HSA) as well as a Flexible Spending Account (FSA) for healthcare, dependent child care, and/or commuting expenses as allowable under IRS guidelines.
• Benefits offerings vary in Puerto Rico.
• Part-time employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company's 401(k) Retirement Plan with employer matching.
• Full-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company's 401(k) program with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance.
• Part-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year).
• All US employees who work in a state or locality with more generous paid sick leave benefits than specified here will receive the benefit of those sick leave laws.

#UST

Skills

• C
• C++
• SystemVerilog
• UVM
• SoC Architecture
• Emulation
• AHB
• AXI
• Cadence Xcelium
• Coverage Modeling
• DDR

Benefits

Compensation range: $ 101,000.00 to 152,000.00 per year

As part of our recruitment process, UST may use AI or automated tools to support activities such as application screening, scheduling, or interview assistance. All hiring decisions are made by our recruitment team. Where applicable law requires it, further notice will be provided separately.

Equal Employment Opportunity Statement

UST is an Equal Opportunity Employer.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, status as a protected veteran, or any other applicable characteristics protected by law. We will consider qualified applicants with arrest or conviction records in accordance with state and local laws and "fair chance" ordinances.

UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.