SoC Debug Tools Engineer — AI-Driven Silicon Validation

Apple Inc.; Cupertino, Northern (CA, KY); Hybrid; USD 216,000 - 394,000; Full time

Benefits offered by this job

Employee stock purchase plan

Restricted stock units (RSUs)

Relocation support

Medical and dental coverage

Education reimbursement

Job summary

Apple Inc. in Cupertino, California, is seeking an engineer to design, build, and enhance silicon debug tools used across hundreds of engineers. You will work across frontend, backend, and data layers while applying AI/ML to accelerate debug workflows and triage intelligence.

The role emphasizes collaboration across hardware, software, and operations, with opportunities to influence the roadmap and drive shift-left strategies in the silicon development cycle.

Qualifications

• Bachelor's degree and 20+ years of relevant industry experience.

Responsibilities

• Design, build, and enhance silicon debug tools spanning automated feature extraction, data collation, visualization, and analysis.
• Drive rapid, targeted debug and triage workflows for engineers across the silicon pipeline.
• Contribute to frontend, backend, and data layers within a professional engineering environment.
• Explore shift-left strategies to surface issues earlier in the silicon development cycle.
• Leverage AI/ML in engineering workflows to accelerate debug and triage intelligence.
• Identify new development opportunities and contribute ideas to the roadmap.

Skills

Cross-disciplinary collaboration

Problem solving

Full-stack instincts

Education

Bachelor's degree

Tools

C

Python

SystemVerilog

SQL/Databases

DFX

Job description

Apple Inc. in Cupertino, California, is seeking an engineer to design, build, and enhance silicon debug tools used across hundreds of engineers. You will work across frontend, backend, and data layers while applying AI/ML to accelerate debug workflows and triage intelligence.

The role emphasizes collaboration across hardware, software, and operations, with opportunities to influence the roadmap and drive shift-left strategies in the silicon development cycle.