Signal Integrity Design Intern – Silicon Valley

Celestica; San Jose (CA); On-site; USD 33,000 - 41,000; Full time

Benefits offered by this job

Development programs

Volunteer days off

Job summary

Celestica is seeking a Signal Integrity Engineering Intern in Silicon Valley for a 3-month internship. You will gain hands-on experience in planning, simulation, lab verification, and troubleshooting of digital PCB designs, while working with global cross-functional teams.

You will learn to research system ideas, support schematic capture, and validate electrical systems from the early design phases through manufacturing support. Start May/June 2027, location Silicon Valley.

Qualifications

• Pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, in their third year of study.
• Foundational knowledge of signal integrity, power integrity, and high-speed PCB design principles.
• Familiarity with SI/PI simulation tools and lab measurement equipment.

Responsibilities

• Design Support: contribute to architectures, schematics, and BOMs for electrical systems.
• Simulation & Analysis: perform SI/PI simulations to evaluate trade-offs.
• Lab Verification: assist in testing high-speed interfaces and compare with simulations.
• Compliance Testing: support testing to meet industry standards.
• Cross-Functional Collaboration: review designs with manufacturing, industrial design, and project leadership.
• Documentation: maintain technical reports and project updates.

Skills

Signal Integrity

Power Integrity

High-speed PCB

Team Collaboration

Education

Bachelor's Degree in Electrical/Electrical Engineering or related (3rd year)

Tools

Keysight ADS

ANSYS HFSS

Synopsys Hspice

Cadence Sigrity

SiWave

HyperLynx

Power SI

Job description

Celestica is seeking a Signal Integrity Engineering Intern in Silicon Valley for a 3-month internship. You will gain hands-on experience in planning, simulation, lab verification, and troubleshooting of digital PCB designs, while working with global cross-functional teams.

You will learn to research system ideas, support schematic capture, and validate electrical systems from the early design phases through manufacturing support. Start May/June 2027, location Silicon Valley.