Signal and Power Integrity Technical Leader (Remote)

Cisco Systems, Inc.; San Jose (CA); Hybrid; USD 214,000 - 310,000; Full time

Job summary

Cisco Silicon One is seeking a Signal and Power Integrity Technical Leader in San Jose to drive ASIC packaging, SI/PI analysis, and high-speed interconnect design. You will lead a team to define rules, verify designs, and collaborate with layout and system partners to achieve optimal performance and reliability.

The role requires extensive lab work, ASIC tape-out experience, and expertise in PAM4, SerDes, and 2.5D packaging.

Qualifications

• Bachelor's degree in Electrical Engineering with 10+ years of SI/PI experience, or advanced degrees with progressive experience.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Experience with 56G PAM4+, SerDes, channel modeling, BER prediction, and high-frequency electromagnetics.
• Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
• Experience with SPICE and practical lab validation.

Responsibilities

• Define, design and verify ASIC packaging for Cisco platforms, guiding SI/PI effort.
• Develop and document rules for ultra-high-speed signaling meeting power, performance, and area goals.
• Analyze substrate SI/PI and coordinate with layout to optimize interposer, substrate and PCB."
• Design, document and develop ASIC packages for high-volume, high-quality release including post-layout extraction.
• Collaborate with system partners to resolve complex IP-level SI/PI issues using advanced rules.
• Lead architecture discussions and contribute to high-performance ASIC/package development.
• Mentor the SI team and promote design reviews and continuous improvement across related teams.

Skills

Signal integrity

Power integrity

High-speed ASIC design

Tape-outs

56G PAM4

SerDes architectures

Channel modeling

BER prediction

Electromagnetics

SPICE

Lab experience

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

Raptor-X

MATLAB

Python scripting

Vector Network Analysis

IBIS

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

SPICE

Raptor-X

MATLAB

Python scripting

Vector Network Analysis

IBIS

Job description

The application window is expected to close on: 12/30/2026

This role is based in our San Jose, CA office, with a preference for candidates who can commute onsite 4-5 days per week. We are open to considering candidates for fully remote work.

Meet the Team

Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world's most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry!

Your Impact

• We are seeking a highly qualified Signal and Power Integrity Technical Leader to help us develop our next generation ASIC packaging and lead our Silicon Packaging Signal and Power Integrity Team to define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.
• Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
• Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
• Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.
• Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
• Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
• Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering and 10+ years of relevant signal and/or power integrity experience, or Master's degree in Electrical Engineering and 8+ years of relevant signal and/or power integrity experience, or PhD in Electrical Engineering and 5+ years of relevant signal and/or power integrity experience.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Experience with 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics with a solid understanding of scattering and impedance network parameters.
• Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
• Experience with SPICE.

Preferred Qualifications

• Experience leading small to medium technical teams.
• Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
• Experience with advanced nodes (5nm, 3nm and below).
• Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
• Experience with die-to-die interfaces (UCIe or proprietary).
• Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
• Experience with MATLAB or Python scripting.
• Experience with Raptor-X.
• Experience with Vector Network Analysis.
• Experience with IBIS.

Why Cisco?

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $214,100.00 to $309,800.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco's policies:

• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees

• 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco

• Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees

• Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)

• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours ofunused sick timecarried forwardfrom one calendar yearto the next

• Additional paid time away may be requested to deal with critical or emergency issues for family members

• Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

• .75% of incentive target for each 1% of revenue attainment up to 50% of quota;

• 1.5% of incentive target for each 1% of attainment between 50% and 75%;

• 1% of incentive target for each 1% of attainment between 75% and 100%; and

• Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$214,100.00 - $356,300.00

Non-Metro New York state & Washington state:

$192,400.00 - $317,200.00

* For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.