Senior Verification Engineer - Analog & Mixed-Signal

Texas Instruments; Santa Clara (CA); On-site; USD 125,000 - 282,000; Full time

Benefits offered by this job

Competitive compensation

Career development opportunities

Diversity and inclusion

Job summary

Texas Instruments is seeking a Design Verification Engineer to verify analog and mixed-signal designs prior to mask development. You will analyze equipment, run simulations, and ensure designs meet specifications while collaborating with product teams and vendors.

The role requires a BS in engineering and 8+ years of experience, with proficiency in UVM, Verilog/SystemVerilog, and Python. You will help drive verification strategy, mentor junior engineers, and participate in reviews to improve

Qualifications

• Bachelor's degree in electrical engineering or equivalent.
• 8+ years of experience in design verification or related field.
• Experience with verification strategies and testbenches is required.
• Strong communication and collaboration skills for cross-functional work.
• Ability to mentor junior engineers and contribute to methodology improvements.

Responsibilities

• Verify accuracy of analog and mixed-signal designs before mask generation.
• Run software simulations and analyze results against specifications.
• Review vendor capabilities to support product development.
• Develop verification strategies and build scalable UVM-based testbenches.
• Participate in code and testbench reviews; drive coverage to closure.

Skills

Analytical skills

Team collaboration

Customer communication

Problem solving

Mentoring juniors

Project delivery

Fast adaptation

Education

Bachelor's degree in Electrical Engineering

Tools

UVM

Verilog

SystemVerilog

Python

EDA tools

UNIX

Job description

Texas Instruments is seeking a Design Verification Engineer to verify analog and mixed-signal designs prior to mask development. You will analyze equipment, run simulations, and ensure designs meet specifications while collaborating with product teams and vendors.

The role requires a BS in engineering and 8+ years of experience, with proficiency in UVM, Verilog/SystemVerilog, and Python. You will help drive verification strategy, mentor junior engineers, and participate in reviews to improve