Senior Test Engineer, CMOS Backplane, Raxium

Google Inc.; Fremont, Northern (CA, KY); Hybrid; USD 159,000 - 230,000; Full time

Job summary

Google Fremont, CA is seeking a Senior Test Engineer for CMOS Backplane development. You will design and validate test standards for microLED displays, work with wafer-level probes and instrumentation, and drive automated testing to meet production and R&D needs.

The role requires strong background in CMOS/silicon testing, programming in C/C++/Python, data analysis, and familiarity with lab equipment. English is required for global collaboration.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering, Physics, or related field, or equivalent experience.
• 4+ years in Silicon/CMOS/IC test development and 3+ years in silicon test hardware, debugging, and data analysis.

Responsibilities

• Develop, validate, and optimize CMOS backplane test solutions for microLED displays.
• Interface with wafer-level probe cards and test equipment for CMOS/Silicon testing.
• Diagnose electrical issues during wafer-level testing using oscilloscopes and equipment.
• Collaborate to define high-speed automated test solutions and reduce test cost.
• Enhance test frameworks based on Reliability Team requirements.

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field

Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field

Tools

Python

SQL

Linux

Ubuntu

C/C++

I2C

SPI

Digital oscilloscope

Power supply

Data analysis

Job description

Senior Test Engineer, CMOS Backplane, Raxium

Google Fremont, CA, USA

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.
• 4 years of experience with Silicon, CMOS, and IC test development.
• 3 years of experience with Silicon test hardware, software debugging, and data analysis in a Research and Development (R&D) or manufacturing environment.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field (e.g., Optics, Sensors, Audio/DSP).
• Experience with testing software development, Python, and SQL databases, and familiarity with Linux and Ubuntu.
• Familiarity with test instruments such as power supply, current meter, voltage meter, digital meter, spectrometer, and other electrical lab equipment.
• Familiarity with firmware concepts, low-level register programming (bare metal programming in C/C++ for microcontrollers), I2C and SPI, and SRAM memory test patterns.
• Knowledge of electrical engineering fundamentals (CMOS and register-level understanding), power management, display architecture, and video standards (e.g., HDMI or MIPI).

About the job

Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google .

• Develop, validate, optimize standards and engineering CMOS Backplane test solutions for microLED display panels, including CMOS control software solutions. Ensure software test platform and architecture meet the needs of fast moving production and R&D environments.
• Interface with wafer-level probe cards, test equipment, and instrumentation to facilitate Complementary Metal-Oxide-Semiconductor (CMOS)/Silicon testing and characterization.
• Identify, diagnose, resolve electrical issues during wafer-level testing using digital oscilloscopes and other testing equipment.
• Collaborate with CMOS and panel test engineering teams to define and implement high-speed, automated testing solutions for IC/Silicon/CMOS and microLED displays, and debug process plans for manufacturing. Optimize these solutions to ensure test coverage and minimize the test cost.
• Work with the Test Engineering team to enhance and develop test frameworks based on requirements from the Reliability Team.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.