Senior System Software Engineer, SoC Power and Performance - O-RAN Infrastructure

NVIDIA Corporation; Santa Clara (CA); On-site; USD 152,000 - 242,000; Full time

Job summary

NVIDIA Corporation seeks an experienced systems engineer to design, develop, and optimize SoC-related software and firmware for O-RAN and cellular infrastructure in Santa Clara. You will work across CPU, GPU, accelerator, memory, interconnect, and I/O subsystems to improve performance and power efficiency.

Expect hands-on work with pre- and post-silicon validation, workload analysis, and DVFS-based optimizations. Strong C/C++ and Python skills, plus Linux kernel experience, are required.

Qualifications

• Bachelor’s or Master’s degree in CS/CE/EE or equivalent experience.
• 5+ years of relevant experience in system software, embedded software, firmware, computer architecture, cellular infrastructure, or performance engineering.
• Experience developing and debugging software for complex SoCs or embedded platforms.
• Strong programming skills in C or C++, and Python or scripting language.
• Deep understanding of computer architecture and hardware-software interaction, including multicore systems and memory hierarchies.
• Experience with OS internals, Linux kernel development, device drivers, concurrency, virtualization, and real-time programming.
• Hands-on expertise in performance measurement, workload characterization, data analysis, bottleneck identification, and system optimization.
• Knowledge of SoC power-management concepts (DVFS, clock/power gating, thermal management).

Responsibilities

• Design, develop, test, and optimize system software and firmware for SoCs used in O-RAN and cellular infrastructure.
• Develop power-management policies and performance optimizations across CPU, GPU, accelerator, memory, interconnect, I/O, and networking subsystems.
• Analyze representative RU and DU workloads to identify architectural and system-level bottlenecks, including compute, memory bandwidth, latency, synchronization, and data-movement constraints.
• Develop and tune power-management capabilities such as dynamic voltage and frequency scaling, clock and power gating, idle-state management, thermal controls, and system-level power budgeting.
• Create performance and power models, measurement tools, benchmarks, and automated test infrastructure for both pre-silicon and post-silicon environments.
• Use simulation, emulation, prototyping, and production silicon to validate architectural decisions and identify power and performance issues.
• Evaluate system behavior against O-RAN and cellular-interface requirements, including timing, synchronization, latency, throughput, and reliability.
• Influence future SoC, platform, and cellular-software architectures based on workload analysis and measurements from deployed systems.

Skills

C/C++

Python

Linux kernel development

Performance engineering

Embedded software

System architecture

Multicore systems

Memory hierarchies

DVFS / power management

O-RAN / Open Fronthaul knowledge

Education

Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or related field

Tools

DPDK

Open Fronthaul

eCPRI

SR-IOV

Linux device drivers

Job description

What you’ll be doing:

• Design, develop, test, and optimize system software and firmware for SoCs used in O-RAN and cellular infrastructure.
• Develop power-management policies and performance optimizations across CPU, GPU, accelerator, memory, interconnect, I/O, and networking subsystems.
• Analyze representative RU and DU workloads to identify architectural and system-level bottlenecks, including compute, memory bandwidth, latency, synchronization, and data-movement constraints.
• Develop and tune power-management capabilities such as dynamic voltage and frequency scaling, clock and power gating, idle-state management, thermal controls, and system-level power budgeting.
• Create performance and power models, measurement tools, benchmarks, and automated test infrastructure for both pre-silicon and post-silicon environments.
• Use simulation, emulation, prototyping, and production silicon to validate architectural decisions and identify power and performance issues.
• Evaluate system behavior against O-RAN and cellular-interface requirements, including timing, synchronization, latency, throughput, and reliability.
• Influence future SoC, platform, and cellular-software architectures based on workload analysis and measurements from deployed systems.

What we need to see:

• Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent experience.
• 5+ years of relevant experience in system software, embedded software, firmware, computer architecture, cellular infrastructure, or performance engineering.
• Demonstrated experience developing and debugging software for complex SoCs or embedded platforms.
• Strong programming skills in C or C++, along with proficiency in Python or a comparable scripting language.
• Strong understanding of computer architecture and hardware-software interaction, including multicore systems, memory hierarchies, caches, interconnects, interrupts, memory-mapped I/O, and DMA.
• Experience with operating-system internals, Linux kernel development, device drivers, concurrency, virtual memory, and real-time or latency-sensitive programming.
• Hands-on expertise in performance measurement, workload characterization, data analysis, bottleneck identification, and system optimization.
• Working knowledge of SoC power-management concepts, including DVFS, clock and power gating, thermal management, and power/performance budgeting.
• A strong grasp of cellular infrastructure and radio-access-network architecture is expected.
• Required knowledge of interface standards relevant to 5G and the evolution toward 6G, such as 3GPP NR interfaces and protocols, O-RAN Open Fronthaul, eCPRI, synchronization and timing technologies, or comparable standards.

Ways to stand out from the crowd:

• Direct experience developing or optimizing software for an O-RAN Radio Unit, Distributed Unit, or both.
• Experience with O-RAN Alliance specifications, including Open Fronthaul control, user, synchronization, and management-plane behavior.
• Familiarity with DPDK, accelerated networking, zero-copy data paths, SR-IOV, RDMA, SmartNICs, DPUs, GPUs, or dedicated baseband accelerators.
• Experience analyzing real-time cellular workloads and optimizing tail latency, jitter, memory bandwidth, cache behavior, and end-to-end performance per watt.
• Experience developing profiling, telemetry, benchmarking, or automated regression tools for power and performance.

Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 152,000 USD - 241,500 USD. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until August 8, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry. Learn more about NVIDIA.