Senior System Integration Engineer, Memory

Nvidia Corporation; Santa Clara (CA); Hybrid; USD 196,000 - 311,000; Full time

Job summary

NVIDIA is seeking a senior Memory Systems Engineer in Santa Clara, CA to lead complex memory subsystem bringup, validation, and characterization across HBM/LPDDR technologies. You will own end-to-end memory closure including performance, power, and reliability, collaborating with design, firmware, and validation teams to ensure robust, scalable products.

The role requires deep expertise in memory training, margining, and cross-domain problem solving, with a system-level instinct to anticipate

Qualifications

• BS or MS in EE/CE or equivalent experience.
• 12+ years in HBM/LPDDR or high-speed memory systems with hands-on silicon bringup, characterization, and debug at scale.
• Deep command of SI/PI, timing, margining, and memory training behavior.
• System-level instinct to foresee memory behavior becoming a product problem and resolve it proactively.

Responsibilities

• HBM & LPDDR System Integration and Bringup: drive bringup, characterization, and debug for next-gen SoCs across memory subsystems.
• Full-Stack Memory Closure: own memory performance, power, thermal, and reliability closure across silicon, package, board, and firmware.
• Post-Silicon Margining, VF Shmoo & Correlation: lead margining and correlation work across voltage, temperature, and frequency.
• Memory Debug: training, calibration, SI/PI & stability issues and cross-domain resolution.
• Validation & Characterization Planning: define validation and issue-tracking plans across chip programs.

Skills

Memory systems engineering

SI/PI & timing

Memory training behavior

Education

BS/MS in EE/CE

Job description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology and amazing people. Today, we're harnessing the boundless possibilities of AI to build the next era of computing. An era in which our GPU acts as the brain of computers, robots, and self-driving cars that can understand the world. Accomplishing unprecedented goals calls for imagination, inventiveness, and exceptional talent from around the world. As a NVIDIAN, you'll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Join our team and discover how you can build a lasting impact on the world.

NVIDIA's Silicon Co-Design Group (SCG) leads the full product development lifecycle, from early architecture definition through silicon bringup to product release. The ArchDev team is the hub for silicon and system-level feature development, driving tradeoff analysis, system integration, and POR alignment across the entire organization. This is where ideas become chips, and chips become products that define the state of the art - and we're building that future with some of the most motivated engineers in the industry.

What you'll be doing:

• HBM & LPDDR System Integration and Bringup: Drive HBM and LPDDR system integration, bringup, characterization, and debug for next-generation SoCs - taking memory subsystems through the full arc from first silicon to production-ready at scale.
• Full-Stack Memory Closure: Own memory performance, power management, thermal, and reliability closure across silicon, package, board, and firmware - translating characterization results into signed-off operating points and release criteria that the full program depends on.
• Post-Silicon Margining, VF Shmoo & Correlation: Lead post-silicon margining, VF shmoo, eye, and correlation work across voltage, temperature, and frequency - building the characterization foundation that underpins every product decision downstream.
• Memory Debug: Training, Calibration, SI/PI & Stability: Debug and resolve memory training, calibration, SI/PI, and system-level stability issues - the class of problems that sit at the intersection of electrical, physical, and software behavior and demand deep cross-domain expertise to resolve at scale.
• Validation & Characterization Planning: Define validation, characterization, and issue-tracking plans across chip programs - building the framework that ensures the right tests exist, the right data gets collected, and issues are tracked with enough fidelity to close.

What we need to see:

• BS or MS in EE/CE - or equivalent experience.
• 12+ years in HBM, LPDDR, or high-speed memory systems, with hands-on depth in silicon bringup, characterization, and debug at scale. PHY controller development experience is a significant plus and will set you apart.
• Deep command of SI/PI, timing, margining, and memory training behavior - and the multi-functional fluency to work across design, package, firmware, validation, and product teams without losing the thread.
• HBM PHY and controller architecture familiarity is useful context, but what this role actually demands is rarer: the system-level instinct to see where memory behavior is about to become a product problem - and the inventiveness to resolve it before it does.

Ways to stand out from the crowd:

• AI-Accelerated Debug & Root Cause Analysis: Use LLM-assisted tools and ML models to pattern-match failure signatures across VF shmoo, eye diagrams, and margining datasets - converging on root cause and outlier detection faster than manual triage, with engineering judgment setting the bar for what the model can decide.
• Experience with HBM3/HBM3E specifics, specific JEDEC margins, thermal-electrical co-sim, ECC methodology & power management is highly desired.
• Intelligent Test & Validation Automation: Automate data collection, test sequencing, and results analysis across characterization programs - cutting cycle time from silicon arrival to product-ready data and freeing bandwidth for problems that require human expertise.
• LLM-Assisted Architecture & Trade-Off Exploration: Accelerate architecture exploration, spec navigation, and cross-domain trade-off analysis using LLMs - surfacing precedents from prior programs and building characterization plans for expert review.

Memory is where performance lives or dies. At the power densities and bandwidths NVIDIA's next-generation SoCs demand, memory systems engineering is one of the most consequential disciplines on the chip. The engineer in this role will have direct influence over whether products meet their performance, power, and reliability targets - and will resolve those challenges alongside some of the most motivated memory and silicon teams in the industry. We're building an encouraging environment where inventiveness is expected, and impact is real. If this is the level you want to operate at, we'd like to hear from you.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 196,000 USD - 310,500 USD.

You will also be eligible for equity and benefits .

Applications for this job will be accepted at least until August 10, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.