Senior Staff Formal Verification Engineer

Qualcomm; Austin (TX); On-site; USD 195,200 - 325,000; Full time

Benefits offered by this job

Discretionary bonus program

RSU grants

Comprehensive benefits package

Job summary

A leading technology firm in Austin is seeking an experienced engineer for the GPU ASICS team. The role involves synthesizing Verilog RTL, implementing hardware emulators, and working with design teams to ensure high-quality outputs. Candidates should hold a degree in Computer Engineering or related fields and have significant experience in software and hardware engineering. The position offers a lucrative pay range between $195,200 and $325,000, along with bonuses and comprehensive benefits.

Qualifications

• 6+ years of relevant experience in Software Engineering, Hardware Engineering, or related fields.
• Experience with hardware emulator platforms and digital design.
• Proficient in design debug and assertion development.

Responsibilities

• Synthesize Verilog RTL and create models for emulators.
• Develop aspects of hardware emulator implementation.
• Drive debug failures on emulator using latest technologies.
• Work on third-party IP integration and system-level debugging.
• Support chip bring-up and post-silicon debug.

Skills

Verilog RTL synthesis

Debugging

Formal verification methodologies

C/C++ Programming

Scripting in Python

Education

Bachelor's degree in Computer Engineering or related field

Master's degree in Computer Engineering or related field

PhD in Computer Engineering or related field

Tools

Palladium

Veloce

FPGAs

Job description

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > GPU ASICS Engineering

General Summary

QCT's Digital ASIC design team delivers cutting edge hardware and software products that power the user experience and graphics content of the most advanced mobile devices on the market.

Graphics formal verification positions involve developing high‑quality formal verification test benches to verify complex designs in GPU.

The position involves working with design and implementation teams to verify designs with high quality, requiring proficiency in debugging, deep bug hunting, formal tools, formal verification methodologies and processes. Candidates should also be proficient in design debug and assertion development.

Minimum Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 6+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 5+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

Job Description

• Synthesize the Verilog RTL and create models and compile them to emulators like Veloce, Palladium, Zebu and/or FPGA platforms.
• Develop all aspects of hardware emulator implementation, with emphasis on design partitioning, synthesis, place and route, timing analysis and run‑time performance.
• Drive debug failures on emulator using latest technologies; work with designers and SW driver team for test plan and debug.
• Work with tool vendors and push the methodology to improve area/performance of the synthesized FPGA RTL.
• Work on third‑party IP integration and system‑level debugging.
• Perform system‑level RTL simulation and design verification.
• Support chip bring‑up and post‑silicon debug.
• Debug functional and timing models.

Preferred Qualifications

• Bachelor’s degree in Science, Engineering, or closely related field.
• 1+ years of hands‑on experience in emulation/simulation acceleration/FPGA.
• 1+ years in Design validation/Post‑Silicon debug.
• 1+ years of hands‑on experience creating high‑performance & area‑efficient emulation environments from RTL.
• 1+ years of hands‑on experience with emulator platforms, platform bring‑up, digital design, verification, debugging, and waveform viewers.
• Experience with hardware emulators such as Palladium, ZeBu, Veloce, or FPGA systems based on Xilinx or Altera FPGAs.
• Experience with emulation methodologies, including in‑circuit emulation, hybrid systems, or simulation acceleration.

Desirable Skills

• MS degree in Electrical Engineering or equivalent; 1 year of practical experience.
• Design Verification knowledge – UVM/SystemVerilog preferred.
• Knowledge of GPU/CPU/DDR/Bus preferred.
• Verilog and SystemVerilog experience.
• Debugging system‑level software, debugging RTL.
• Programming skills in C and C++.
• Scripting in Python, Tcl, or Perl.
• Knowledge of Vendor Emulation tools, Xilinx tools, Synthesis tools.

EEO Statement

QQQ is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Pay Range and Benefits

Pay Range: $195,200.00 – $325,000.00. The company also offers a competitive annual discretionary bonus program, RSU grants, and a comprehensive benefits package.