Senior Staff Design Verification Engineer - AI Chip

Cerebras Systems; Sunnyvale (CA); On-site; USD 250,000 - 300,000; Full time

Job summary

Cerebras Systems in Sunnyvale, CA, is seeking a Design Verification professional to join our team building the world's largest AI chip. You will work with architects, RTL, firmware and validation to ensure silicon-first verification and robust testbenches.

You will develop verification strategies, reusable environments, and scalable testbenches, while debugging complex issues across simulation, emulation, and bring-up phases. A strong background in SystemVerilog, UVM, and Python is essential.

Qualifications

• 15+ years of Design Verification experience.
• BS or MS in Computer Science or Electrical Engineering.
• Deep knowledge of SystemVerilog testbench, DPI and UVM.
• Proficient in Python or Perl scripting.
• Experience developing scalable and portable testbenches and components.
• Experience with verification methodologies and tools (simulators, waveform viewers, automation, coverage).
• Excellent programming skills and software engineering practices (OO design).
• Great debugging, problem-solving and teamwork abilities.

Responsibilities

• Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works first silicon.
• Develop and implement verification strategies, detailed tests and coverage plans based on micro-architecture.
• Create verification methodologies and reusable environments, including stimulus, checkers, assertions, and coverage.
• Implement tests, manage regressions, gather coverage, and debug test failures.
• Collaborate with cross-functional teams including architecture, RTL design, physical design, firmware, and validation.
• Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases.
• Continuously enhance verification infrastructure and flows to improve efficiency and quality.
• Contribute to the evolution of verification methodology and best practices.

Skills

SystemVerilog

UVM

DPI

Python

Perl

OO design

Debugging

Problem solving

Self-motivated

Education

BS or MS in CS or EE

15+ years of Design Verification experience

Tools

Simulators

Waveform viewers

Build and run automation

Coverage collection

Gate level simulations

Job description

Cerebras Systems in Sunnyvale, CA, is seeking a Design Verification professional to join our team building the world's largest AI chip. You will work with architects, RTL, firmware and validation to ensure silicon-first verification and robust testbenches.

You will develop verification strategies, reusable environments, and scalable testbenches, while debugging complex issues across simulation, emulation, and bring-up phases. A strong background in SystemVerilog, UVM, and Python is essential.