Senior Staff ASIC Physical Design Engineer

Northrop Grumman Corporation; Maryland; On-site; USD 197,000 - 297,000; Full time

Job summary

A leading aerospace and defense company in Maryland is seeking an experienced ASIC Design Engineer to oversee the physical implementation of ASIC designs. This role includes leading a team of engineers, performing design tasks, and collaborating with front-end teams. Ideal candidates will have significant experience in backend ASIC design and must be U.S. citizens. Competitive salary and benefits offered.

Benefits

Health insurance

Life and disability insurance

Paid time off (PTO)

Qualifications

• Bachelor’s degree with 14 years of experience, or a Master's with 12 years.
• Proficient in backend ASIC design including synthesis and static timing analysis.
• Ability to obtain and maintain the necessary U.S. Government security clearance.

Responsibilities

• Responsible for the complete physical implementation at block and chip levels.
• Lead team of ASIC engineers to meet design requirements and schedule.
• Collaborate with the front-end team to resolve design issues.

Skills

Backend ASIC design

Scripting languages (Tcl, Python, Perl)

Communication skills

Technical problem solving

Education

Bachelor’s degree in a relevant field

Master’s degree in Electrical Engineering

Tools

Cadence ASIC toolset

Siemens ASIC toolset

Job description

RELOCATION ASSISTANCE: Relocation assistance may be available.
Clearance Type: Polygraph.
Travel: Yes, 10% of the Time.

Overview

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history — from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.

Roles and Responsibilities

• Responsible for the complete physical implementation at both block and chip levels.
• Perform physical design of ASIC designs, including floor planning, placement and routing, clock tree synthesis, physical verification, and IR/EM analysis.
• Ensure the final physical implementation meets all design requirements.
• Lead team of ASIC engineers to meet design requirements and the schedule.
• Collaborate with the front-end team to address and resolve design issues and challenges.
• Develop automation and flow enhancements to improve processes and implementation efficiencies.
• Report ASIC physical design status to the project leadership.

Basic Qualifications

• Bachelor’s degree with 14 years of experience, a Master’s degree with 12 years of experience or a PhD with 9 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree.
• U.S. Citizenship is required.
• The ability to obtain/maintain an Active DoD Secret clearance.
• Experience in full product life cycle of ASIC Design.
• Proficient in backend ASIC design including synthesis and static timing analysis, place and route, physical verification (LVS/DRC).
• Proficient with Cadence and Siemens ASIC toolset e.g., Innovus, Genus, Tempus, Calibre, etc.
• Has working knowledge in HDL (VHDL/Verilog).
• Proficient in scripting languages such as Tcl, Python or Perl.
• Knowledge of DFT, including scan insertion and ATP.
• Effective communication and presentation skills and high proficiency in technical problem solving.
• This position requires the applicant to be a U.S. Citizen.
• Ability to obtain and maintain the necessary U.S. Government security clearance per customers’ requirements.

Preferred Qualifications

• Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields.
• Experience with multiple tapeouts with advanced technology nodes (sub 12nm).
• Experience with multiple tapeouts with GlobalFoundries, TSMC or Intel foundries.
• Experience with leading teams to deliver working silicon.
• Active U.S. government TS security clearance.

Primary Level Salary Range: $197,500.00 - $296,300.00. The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions. Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business. The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.

Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.