Senior SoC Architect - Embedded AI Accelerators

Advanced Micro Devices; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD is seeking a Senior SoC Architect in San Jose, CA, to define next‑generation adaptive and embedded SoCs. You’ll drive architecture across embedded processing subsystems, memory controllers, and FPGA fabric, collaborating with customers, product planning, and design teams.

You will shape power- and performance-optimized architectures for AI/ML, data center, automotive, and aerospace applications, while guiding pre- and post-silicon activities and ensuring architectural consistency with

Qualifications

• Experience architecting SoCs with processor, accelerator and I/O subsystems.
• Knowledge of cores running x86, RISC-V, or ARM ISA, PCIe and Ethernet.
• Familiarity with boot, security, debug, telemetry and RAS concepts.

Responsibilities

• Drive low-power, cost-optimized SoC architectures with processor, accelerator and I/O subsystems.
• Define SoC architectures with embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric.
• Create modular subsystem architectures deployable in chiplet, monolithic, or 3D form factors.
• Collaborate with customers and cross-functional teams to scope requirements and define architecture meeting PPA and schedule targets.
• Define hardware, software, and firmware interactions between subsystems and accelerators.
• Author architecture specifications and guide pre-silicon and post-silicon validation.

Skills

SoC architecture

Low power design

Embedded systems

Cross-functional collaboration

Education

BS/MS/PhD in electrical or computer engineering

Tools

PCIe

Ethernet

DDR

FPGA

Job description

AMD is seeking a Senior SoC Architect in San Jose, CA, to define next‑generation adaptive and embedded SoCs. You’ll drive architecture across embedded processing subsystems, memory controllers, and FPGA fabric, collaborating with customers, product planning, and design teams.

You will shape power- and performance-optimized architectures for AI/ML, data center, automotive, and aerospace applications, while guiding pre- and post-silicon activities and ensuring architectural consistency with