Senior Silicon Architect for AI Accelerators & Co-Design

Google DeepMind; San Francisco (CA); On-site; USD 256,000 - 278,000; Full time

Job summary

Google DeepMind is seeking a senior hardware engineer to help deliver codesigned, high-performance accelerators. You will deploy new hardware in Google data centers, collaborating with teams across Google's stack to ensure efficient integration of hardware and software, while advancing ML models, numerics, and sparsity.

The role involves a broad scope across architecture, design verification, and physical design, with production-quality outcomes.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 10 years of experience with leading multiple design domains (DFT, DV and Physical Design).
• 5 years of experience with logic design, computer architecture and circuit theory.
• 5 years of experience in power or performance modeling or system performance analysis.

Responsibilities

• Architect, design, and implement hardware for novel systolic array accelerators.
• Own subsystems up to the entire accelerator, carrying the implementation from requirements through tapeout and bringup.
• Collaborate with application, algorithm, and performance-tuning experts to codesign solutions for efficiency and performance.
• Write code for accelerators to meet production requirements at system, library, and application levels.
• Bring a generalist approach to computer systems, interfacing across disciplines.

Skills

Leading multiple design domains

Logic design

Computer architecture

System performance analysis

Power/performance modeling

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Tools

Linux kernel programming

Job description

Google DeepMind is seeking a senior hardware engineer to help deliver codesigned, high-performance accelerators. You will deploy new hardware in Google data centers, collaborating with teams across Google's stack to ensure efficient integration of hardware and software, while advancing ML models, numerics, and sparsity.

The role involves a broad scope across architecture, design verification, and physical design, with production-quality outcomes.