Senior Signal Integrity Engineer, Platforms

Socket.dev; Sunnyvale (CA); On-site; USD 159,000 - 230,000; Full time

Job summary

Google's Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. As a Signal Integrity Engineer, you will design and build the systems that are important to our largest computing infrastructure, guiding concepts through high-volume manufacturing.

You will see those systems from concepts to manufacturing, ensuring margins and performance across data center hardware.

Qualifications

• Bachelor’s degree or equivalent practical experience in a relevant field.
• 4 years of SI-related experience or 3 years with advanced degree.
• Experience with lab validation and product development processes.

Responsibilities

• Support System Signal Integrity (SI) design on data center hardware products.
• Collaborate with board, chip and system engineers, design partners, and chip vendors to support system SI design, explore layout and manufacturability tradeoffs, and ensure that product functions as required.
• Support Application-Specific Integrated Circuit (ASIC), package, board, connector, and cable vendors to develop new interconnect technologies.
• Participate in system interconnects bring up and qualification, work with test engineers and include configuring chips to ensure adequate margin.
• Collaborate with design engineers, Printed Circuit Board (PCB) designers, and system teams to help solve SI issues.

Skills

Signal Integrity

Lab validation

Technical leadership

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or related field

Tools

Allegro

HFSS

SIwave

ADS

MATLAB

PowerDC

PowerSI

Python

Bash

Job description

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
  
• 4 years of experience working in a signal integrity technical environment, or 3 years of experience with an advanced degree.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field.
• 1 year of experience in technical leadership.
  
• Experience with the product development process for mass volume production design, with a focus on signal integrity, power integrity and lab validation.
• Experience with PCIE, DDR, SATA, ethernet standards, PCB, connector, or cable design and assembly processes, including materials and component selection.
• Experience with Allegro, HFSS, SIwave, ADS, MATLAB, PowerDC, PowerSI, and scripting for data collection and analysis (e.g., Python, Bash).
• Experience in a lab environment with Serializer/Deserializer (SerDes) testing and understanding of SerDes capabilities.
  

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational tests are complex and unique, enabled by custom hardware designed and made in-house.
As a Signal Integrity Engineer, you will design and build the systems that are important to our largest and powerful computing infrastructure. You will see those systems from concepts all the way through to high volume manufacturing. You will support the machinery that goes into our data centers affecting millions of Google users.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by cutting-edge custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concept all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers, affecting millions of Google users.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:

• Support System Signal Integrity (SI) design on data center hardware products.
  
• Collaborate with board, chip and system engineers, design partners, and chip vendors to support system SI design, explore layout and manufacturability tradeoffs, and ensure that product functions as required.
• Support Application-Specific Integrated Circuit (ASIC), package, board, connector, and cable vendors to develop new interconnect technologies.
  
• Participate in system interconnects bring up and qualification, work with test engineers and include configuring chips to ensure adequate margin.
  
• Collaborate with design engineers, Printed Circuit Board (PCB) designers, and system teams to help solve SI issues.