Senior Product Manager, Hardware (NPU IP)

Quadric; Burlingame (CA); On-site; USD 200,000 - 250,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Company‑paid life Insurance

Equity in the business

401(k) Retirement Plan

Flexible PTO

Catered lunch

Job summary

Quadric, based in Burlingame, CA, seeks a Senior Product Manager, Hardware to own the Chimera GPNPU IP roadmap and drive architecture decisions with anchor customers. You will collaborate with Tier‑1 automotive and OEM teams and guide feature sets across multiple tracks for real‑time edge devices.

You will partner with international customers, influence SoC integration, and champion architectural usability. A Bay Area relocation and travel may be required.

Qualifications

• Experience in hardware or silicon product management is required.
• Direct experience in multiple: NPU/AI accelerator architecture, SoC integration, DSP/vector compute, automotive silicon, or semiconductor IP licensing.

Responsibilities

• Own Chimera GPNPU IP roadmap across five tracks: Compute, Efficiency, Scalability, Safety, and Integration.
• Lead architecture reviews with anchor accounts and translate feedback into the roadmap.
• Productize integration and usability knobs to streamline customer IP integration cycles.

Skills

NPU/AI accelerator

SoC integration

DSP/vector compute

automotive silicon

semiconductor IP licensing

agentic AI tools

Education

EE/CE/CS engineering degree

Job description

Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems.

Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world's first supercomputer designed for the real-time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow's technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21.

The Opportunity

Quadric has created an innovative General-Purpose Neural Processing Unit (GPNPU) architecture—the Chimera GPNPU—which executes both neural network inference workloads and conventional C++ DSP code on edge and endpoint devices. As the Senior Product Manager, Hardware, you will own the Chimera GPNPU IP roadmap across five strategic tracks: Compute, Efficiency, Scalability, Safety, and Integration. Setting feature sets for upcoming IP generations, driving architecture freeze decisions, and partnering directly with anchor SoC customer teams worldwide, you'll ensure our silicon IP powers production devices shipping in 2027 and beyond.

What You'll Do

Hardware Roadmap & Architecture Freeze

• Translate customer requirements, competitive pressures, and architectural constraints into track-by-track feature lists with explicit gating.
• Build the business and technical case for contested architecture decisions and lead trade‑off reviews with architects to bring clear recommendations to the Product Steering Committee (PSC).
• Drive IP usability by identifying silent customer workarounds (API wrappers, custom RTL hooks, glue logic) and productizing proper architectural solutions. kernels when required.

Customer Engagement & Technical Ownership

• Serve as the named hardware product owner for key anchor accounts, presenting new features and integrating formal architecture feedback into the product roadmap.
• Conduct architecture reviews with technical buyers, including Tier‑1 automotive and OEM SoC design teams.
• Partner with international customers, particularly supporting key anchor accounts in the Japanese and global semiconductor markets.

Competitive Intelligence & SoC Integration

• Analyze competitive architectures (e.g., Synopsys NPX6, Arm Ethos‑U85, Ceva NeuPro‑M, NVIDIA Jetson) to anticipate market needs and inform product requirements before gaps appear in customer evaluations.
• Define and position SoC integration features, specifying which knobs (AXI4/ACE‑Lite, CoreSight, power domains, performance counters) are exposed and productized.
• Sequence functional safety positioning, lockstep configurations, FMEDA work, and safety‑island architectures for automotive and critical application standards.

What Success Looks Like

• Freeze and lock in next‑generation GPNPU IP feature sets (QC/QD releases) aligned with target customer tape‑out schedules.
• Successfully lead technical architecture reviews with anchor Tier‑1/OEM accounts and convert their feedback into actionable roadmap tracks.
• Productize key integration and usability knobs to streamline customer IP integration cycles.

What We're Looking For

Required

• 5–8 years of Product Management experience focused on hardware or silicon products, with a senior IC background.
• Direct experience in at least two of the following: NPU/AI accelerator architecture, SoC integration, DSP/vector compute, automotive silicon, or semiconductor IP licensing.
• Proven experience leading technical architecture reviews with sophisticated buyers (Tier‑1 automotive, OEM SoC teams).
• Active adoption of agentic AI tools (e.g., Claude Code, Cursor, or equivalent) in daily workflows.
• EE/CE/CS engineering degree (or equivalent depth), based in or willing to relocate to the Bay Area (Burlingame hybrid model), and willing to travel quarterly (domestic and international).

Preferred

• Prior RTL or silicon‑implementation background (e.g., shipped a block, went through tape‑out, or owned a microarchitecture spec).
• Experience working at a semiconductor IP vendor (e.g., Synopsys, Arm, Ceva, Cadence, Imagination, VeriSilicon).
• Direct exposure to AI/ML compute stack architectures (dataflow, quantization, sparsity, mixed‑precision trade‑offs).
• Experience engaging with Japanese‑market customers and technical teams.

What we offer

The base salary range for this position is $200,000 to $250,000. This range reflects the full span of levels and geographies at which Quadric hires for this role. The actual base salary offered will depend on a number of factors, including the specific level of the role, years and depth of relevant experience, technical skills and competencies, the criticality of the role to the business, internal equity, and work location. In addition to base salary, this role is eligible for equity and a discretionary annual performance bonus as applicable to the role and level.

Quadric also offer a variety of benefits to support your needs. The benefits below reflect our US‑based offerings; for roles in other locations, benefits vary and are shared during the hiring process. These include:

• Medical, dental, and vision insurance from day one – Premiums covered at 99% for Employees
• Company‑paid life Insurance
• Voluntary supplemental life insurance
• STD + LTD insurance
• Commuter support including parking or Caltrain reimbursement. Our office is conveniently located within walking distance of the Caltrain station
• FSA + HSA
• Equity with the business
• Paid Parental Leave
• 401(k) Retirement Plan
• Flexible PTO
• Winter holiday shutdown
• Catered lunch each day in our office
• Downtown Burlingame office location, close to shops, cafes, and local amenities
• Collaborative, low-ego culture with significant ownership and impact
• A work culture focused on innovative disruption

Equal Employment Opportunity

Quadric is an equal opportunity employer. We do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, sexual orientation, gender identity, marital status, medical condition, or any other characteristic protected by applicable federal, state, or local law.

E-Verify and Right to Work Notices

Quadric participates in the E-Verify program to confirm employment eligibility for U.S.-based roles. As part of this process, applicants may review the following notices, which explain your rights and our participation in E-Verify. These notices are provided in English and Spanish.

• E-Verify Participation Notice (English | Spanish)
• Right to Work Notice (English | Spanish)

No action is required from candidates during the application process. These notices are provided for informational purposes only.

Privacy

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