Senior Principal Mixed-Signal Verification Architect

Renesaselectronics; Chandler (AZ); On-site; USD 180,000 - 240,000; Full time

Job summary

Renesas Electronics in Chandler, AZ, is seeking a senior verification engineer to design and architect mixed-signal verification environments for PMIC designs, integrating RNM and AMS models, and to develop comprehensive verification plans.

You will lead GLS flows, debug analog and digital blocks, perform RTL and gate-level simulations across PVT corners, and mentor junior engineers while collaborating with Design, ATE, and Silicon Validation teams for seamless handoffs.

Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of experience in mixed-signal or analog circuit verification.
• Hands-on experience with RNM and AMS model integration.
• Proficiency in RTL and behavioral simulation tools (Spectre, Xcelium).
• Strong understanding of GLS flows and debugging GLS simulations.
• Experience with automotive PMIC or power management IC design and verification.
• Proficiency in Verilog, SystemVerilog, and SPICE-based languages.
• Knowledge of UVM, assertions, coverage-driven verification.

Responsibilities

• Design and architect mixed-signal verification environments for PMIC designs.
• Develop verification plans and strategies for automotive PMIC products (ISO 26262, AEC-Q200).
• Set up GLS flows and correlate with RTL simulations to resolve discrepancies.
• Lead debugging of analog blocks (switching regulators, LDOs) and digital RTL.
• Perform RTL and Gate-Level simulations across PVT corners for timing, power, and correctness.
• Collaborate with Design, Applications, ATE and Silicon Validation teams for handoffs.
• Mentor junior verification engineers and define best practices and methodologies.
• Troubleshoot complex design issues involving analog-digital interactions with simulation and measurement techniques.
• Drive tool/methodology improvements and evaluate AI-based verification solutions.
• Create and maintain verification documentation, plans, and coverage metrics.

Skills

Leadership

Mentoring

Problem solving

Debugging

Analytical mindset

Education

MS or PhD in Electrical Engineering, Computer Engineering, or related field

Tools

Spectre

Xcelium

Verilog

SystemVerilog

SPICE

Job description

Renesas Electronics in Chandler, AZ, is seeking a senior verification engineer to design and architect mixed-signal verification environments for PMIC designs, integrating RNM and AMS models, and to develop comprehensive verification plans.

You will lead GLS flows, debug analog and digital blocks, perform RTL and gate-level simulations across PVT corners, and mentor junior engineers while collaborating with Design, ATE, and Silicon Validation teams for seamless handoffs.