Senior Principal Digital Design Architect (ASIC/SoC)

Insight Global; Irvine (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Insight Global in Irvine, CA is seeking a senior ASIC design engineer to define microarchitecture for high-speed subsystems and translate standards into RTL implementations. You will lead cross-functional teams, optimize area, power, and timing, and contribute to verification strategies using UVM.

The role requires deep SystemVerilog/RTL expertise, front-end design experience, and strong problem-solving skills to deliver next-generation data-center SoCs.

Qualifications

• BS or higher with 11+ years of experience in ASIC design.
• Strong expertise in SystemVerilog and RTL coding.
• Experience with front-end design flow including lint, CDC, power analysis, and timing closure.

Responsibilities

• Define microarchitecture for subsystems (e.g., 200/400G Ethernet, PCIe, DSP, FEC).
• Translate standards into RTL implementations and perform area/power/timing optimization.
• Lead cross-functional teams to define product specs, HW/SW partitioning, and execution plans.

Skills

SystemVerilog RTL

UVM verification

High-speed interfaces

Performance modeling

SoC integration

Education

BS in Electrical Engineering or related field

MS or PhD for advanced roles

Tools

Cadence tools

Synopsys tools

UVM

Job description

Insight Global in Irvine, CA is seeking a senior ASIC design engineer to define microarchitecture for high-speed subsystems and translate standards into RTL implementations. You will lead cross-functional teams, optimize area, power, and timing, and contribute to verification strategies using UVM.

The role requires deep SystemVerilog/RTL expertise, front-end design experience, and strong problem-solving skills to deliver next-generation data-center SoCs.