Senior Physical Design Engineer

Samsung Semiconductor Inc.; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks paid time off

Fertility/adoption stipend

Medical travel support

Onsite cafe and gym

Flexible work environment

Job summary

Samsung Semiconductor Inc. in San Jose seeks an experienced physical design engineer to own memory-centric IP and SoC partitions from RTL to GDSII.

You will drive PPA convergence, floorplanning, and timing closure, collaborating with RTL, verification, and foundry teams to deliver efficient, high-performance designs. The role requires 5+ years in physical design, scripting skills, and hands-on use of Synopsys Fusion Compiler, Innovus, PrimeTime, and StarRC.

Qualifications

• Bachelor’s in EE or related field with 5+ years experience in physical design.
• Strong background in digital physical design and VLSI implementation.
• Experience with synthesis, floorplanning, place-and-route, CTS, and timing closure for ASIC/SoC designs.
• Proficiency with EDA tools such as Fusion Compiler/ICC2, Innovus, PrimeTime, StarRC.

Responsibilities

• Own physical implementation of memory-centric IP and SoC partitions from RTL to GDSII.
• Drive PPA convergence and timing closure across corners and modes.
• Develop floorplans, power delivery networks, and macro placement strategies.
• Perform STA, constraint development, and signoff; resolve timing and IR-drop issues.
• Coordinate with RTL, verification, foundry, and library teams for signoff.
• Automate physical design flows using Tcl/Python scripting.
• Communicate with stakeholders to deliver designs on time and within budget.
• Complete other duties as needed.

Skills

Digital physical design

Synthesis

Floorplanning

Place-and-route

Clock tree synthesis

Timing closure

Python scripting

Tcl scripting

AI/ML workloads

Communication

Team collaboration

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical Engineering or related field

Tools

Synopsys Fusion Compiler/ICC2

Cadence Innovus

PrimeTime

StarRC

Job description

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World's Technology Together: Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location: Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You'll Do

• Own the physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII, including synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing.
• Drive block- and full-chip-level PPA (performance, power, and area) convergence and timing closure across multiple process corners and operating modes.
• Develop floorplans, power delivery networks, and macro placement strategies for memory controllers, NoC, and high-bandwidth interconnect subsystems.
• Perform static timing analysis (STA), constraint development, and signoff, resolving setup/hold timing, IR-drop, electromigration, and signal integrity issues.
• Execute physical verification and signoff (DRC, LVS, antenna, and reliability checks) in collaboration with foundry and standard‑cell/memory library teams on advanced process nodes.
• Collaborate with RTL and verification engineers, providing physical feedback that informs design-for-PPA and floorplan‑aware microarchitecture decisions.
• Make design decisions out of a large design trade‑off space across performance, power, thermal, and cost.
• Develop and automate physical implementation flows and methodologies using Tcl/Python scripting and agentic AI tools and frameworks to improve turnaround time and quality of results.
• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the designs are delivered on time and within budget.
• Complete other responsibilities as assigned.

What You Bring

• Bachelor's with 5+ years, or Master's with 3+ years, or PhD's with 0+ years of industry experience.
• Strong background in digital physical design and VLSI implementation.
• 5+ years of experience in physical design implementation - synthesis, floorplanning, place-and‑route, clock tree synthesis, and timing closure - for complex ASIC/SoC designs.
• Proficiency with industry-standard EDA tools such as Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, and StarRC.
• Experience with static timing analysis and constraint (SDC) development, low‑power design (UPF/CPF), and power, IR-drop, and electromigration analysis.
• Experience with physical verification (DRC, LVS, antenna) and tapeout on advanced FinFET process nodes.
• Experience implementing memory controllers, NoC, or high‑speed interconnect IP and full‑chip SoC integration.
• Proficiency in scripting (Tcl, Python, or Perl) for physical design flow automation.
• Experience in AI/ML workloads.
• Strong analytical and problem‑solving skills
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You're inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

What We Offer

• Give Back: With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
• Enjoy Time Away: You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
• Care for Family: Whatever family means to you, we want to support you along the way-including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
• Prioritize Emotional Wellness: With on‑demand apps and free confidential therapy sessions, you'll have support no matter where you are.
• Stay Fit: Eating well and being active are important parts of a healthy life. Our onsite Cafe and gym, plus virtual classes, make it easier.
• Embrace Flexibility: Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.

Base Pay Range

$138,000 — $206,000 USD

Equal Opportunity Employment Policy

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long‑term conditions, neurodivergent individuals, or those requiring pregnancy‑related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

Our Commitment to Innovation and Fairness

At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision‑maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically.

Recruiting Agency Policy

We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.

Applicant AI Use Policy

At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we ask that candidates rely on their own knowledge and skills throughout the process. AI tools may be used for basic preparation, grammar, and research, but should not be used to generate or assist with submitted content or live interview responses. If we determine that AI is being used outside these guidelines, we reserve the right to pause or end the interview, and your candidacy may be disqualified.

Trade Secret Notice

By submitting an application, you agree not to disclose to Samsung-or encourage Samsung to use-any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

Applicant Privacy Policy

Applicant Privacy Policy: https://semiconductor.samsung.com/about-us/careers/us/privacy/