Senior Photonics Engineer

Lyte; Sunnyvale (CA); On-site; USD 210,000 - 280,000; Full time

Benefits offered by this job

Competitive salary

Equity

Health coverage

401(k)

Flexible vacation

Collaborative environment

Cutting-edge tech

Job summary

Lyte, based in Sunnyvale, CA, seeks a senior Photonics Engineer to design silicon photonic devices and PICs for next‑gen perception systems. You will own end‑to‑end design from simulation through tapeout, interfacing with the silicon team for validation and production transfer.

You will simulate, optimize, and validate devices with EM and optical‑circuit tools, develop PDK elements, and contribute to architecture definitions and reproducible workflows in a fast‑paced, cross‑functional

Qualifications

• Advanced degree with 8+ years industry experience.
• Hands-on design of silicon/silicon nitride photonic components with tapeouts.
• Strong waveguide optics and device physics knowledge.
• Proficient in EM and optical-circuit simulations.
• Experience with foundry rules, LVS/DRC and layout tools.
• Python for automation and data analysis.
• Capable of owning designs end‑to‑end and communicating results clearly.

Responsibilities

• Design photonic components and subcircuits for PICs.
• Simulate and optimize performance to meet specs.
• Develop tapeout‑ready layouts and verify LVS/DRC.
• Collaborate with silicon team for test and validation.
• Create design handoffs and documentation for production.
• Automate workflows with Python for simulations and data analysis.

Skills

PhD/MS in EE

5+ years exp

PIC tapeouts

Waveguide optics

EM/optical simulations

Cadence/Synopsys

Python

Version control

Communication skills

Data analysis

Education

MS/PhD in EE/Physics/Optics

BS with equivalent experience

Tools

Cadence

Synopsys

Lumerical

Tidy3D

Job description

About Lyte

Lyte builds perception systems for Physical AI operating in complex environments. The company combines custom silicon, integrated sensors, and software into a unified platform for robotics, mobility, and next-generation automation. Lyte is headquartered in Sunnyvale, California, with a global presence. For more information, visit www.lyte.ai

About Lyte

Lyte builds perception systems for Physical AI operating in complex environments. The company combines custom silicon, integrated sensors, and software into a unified platform for robotics, mobility, and next-generation automation. Lyte is headquartered in Sunnyvale, California, with a global presence. For more information, visit www.lyte.ai If you’re excited about building impactful technology in a dynamic, hands‑on environment, we’d love to hear from you!

About The Role

• We are seeking a senior Photonics Engineer to design silicon photonic devices, subcircuits, and photonic integrated circuits (PICs) for Lyte’s next‑generation perception systems. As a member of the Photonics Design and Architecture team, you will translate architecture‑level requirements, including optical link budgets, component specifications, and interface requirements, into optimized designs, validated simulation models, and tapeout‑ready layouts. This is a hands‑on technical role with end‑to‑end ownership of assigned components and subcircuits, from simulation and layout through design verification, tapeout, and documentation. You will work closely with the silicon team, which owns test and validation, and deliver complete design handoffs that enable transfer to production.

What You’ll Do

• Design photonic components and subcircuits. Design passive and active silicon and silicon nitride devices, including couplers, splitters, interferometers, polarization‑management components, phase shifters, switches, and optical interfaces.
• Simulate and optimize performance. Use electromagnetic, optical‑circuit, and thermal simulation to predict device behavior. Optimize designs against specifications for insertion loss, bandwidth, polarization response, footprint, power, and fabrication tolerance.
• Contribute to architecture definition. Provide device‑level performance models, simulation data, and tradeoff analyses that inform optical link budgets, component specifications, interface requirements, and performance margins.
• Develop tapeout‑ready layouts. Implement component and subcircuit layouts in accordance with foundry design rules, run design‑rule checks, and prepare design files for review and integration into full PIC layouts.
• Verify designs and support tapeout signoff. Evaluate nominal performance, process sensitivity, and operating‑condition limits. Document assumptions, margins, and open risks, and present results in design reviews and cross‑functional tapeout signoff.
• Advance the PDK. Develop and maintain parameterized cells (PCells), compact models, component documentation, and reusable design elements. Update models and design guidance as characterization data become available.
• Automate engineering workflows. Build Python tools for simulation setup, parameter sweeps, optimization, layout generation, and data analysis. Maintain reproducible workflows and version‑controlled design assets.
• Co‑design for optical and system integration. Incorporate requirements for III–V sources, free‑space coupling, packaging, thermal management, and electrical interfaces into device and subcircuit designs. Work with the III–V, packaging, and IC teams to close interface requirements.
• Partner with the silicon team on test and validation. Define test structures, design‑of‑experiment (DOE) splits, and characterization objectives. Provide predicted responses and measurement priorities, interpret results with the silicon team, and use findings to improve designs, models, and the PDK.
• Deliver complete design handoffs. Deliver design files, specifications, simulation results, interface requirements, and functional documentation to the silicon team for production transfer. Support the silicon and operations teams with technical questions and design revisions following handoff.

Required Qualifications

• M.S. or Ph.D. in electrical engineering, physics, optics, or a related discipline, or a B.S. with equivalent industry experience.
• 8+ years of relevant industry experience (or a Ph.D. with 5+).
• Hands‑on experience designing silicon or silicon nitride active and passive photonic components, with design ownership on multiple completed PIC tapeouts.
• Strong understanding of waveguide optics, semiconductor device physics, and fabrication‑dependent device performance.
• Proficiency with electromagnetic simulation methods such as FDTD, eigenmode solvers, and eigenmode expansion (EME), as well as optical‑circuit simulation with Lumerical, Tidy3D or equivalent.
• Experience with schematic driven layout in Cadence or Synopsys, foundry design rules, and pre‑tapeout design verification including LVS/DRC.
• Proficiency in Python for scientific computing, simulation automation, and data analysis.
• Demonstrated ability to independently own designs from specification through tapeout, evaluate tradeoffs, and communicate results clearly to technical and cross‑functional audiences.
• Experience using version control and maintaining organized, reproducible engineering work.

Preferred Qualifications

• Experience developing PCells, compact models, and PDK component libraries.
• Exposure to III–V devices and understanding of lasers, semiconductor optical amplifiers, including hybrid or heterogeneous integration with silicon photonics.
• Exposure to optical packaging, micro‑optics, or free‑space coupling.
• Experience correlating simulated device behavior with measured results.
• Familiarity with statistical variation analysis (e.g., Monte Carlo and corner analysis) and numerical optimization.
• Experience mentoring engineers or leading technical design reviews.

Benefits

(subject to location and local regulations)

• Competitive salary and equity
• Comprehensive medical, dental, and vision coverage
• 401(k) retirement plan
• Flexible vacation and time‑off policy
• Collaborative, fast‑paced, and inclusive work environment
• Opportunity to work on cutting‑edge technologies with a highly cross‑functional team

The Pay Range For This Role Is

210,000 - 280,000 USD per year(Bay Area, CA)