Senior PCB Layout Engineer, Google Cloud

Google LLC; Sunnyvale (CA); On-site; USD 159,000 - 230,000; Full time

Job summary

Google LLC is seeking a Senior PCB Layout Engineer for the Platforms Infrastructure team in Sunnyvale, CA. The role focuses on fast-paced board programs, providing placement and routing support, and interfacing with mechanical and manufacturing engineers throughout the product lifecycle.

The candidate will contribute to the development of hardware for Google's data centers, collaborating with internal teams and external vendors to apply industry standards and best practices in PCB design and

Qualifications

• Bachelor’s degree or higher in a relevant field or equivalent practical experience.
• 4 years PCB design experience, or 3 years with an advanced degree.
• Experience with CAD tools such as OrCAD, Concept, and Allegro.
• Experience with PCB design tools and methodology.

Responsibilities

• Create PCB outline and layer setup, component placement and signal routing.
• Write and maintain scripts related to PCB design, DFM, and release (e.g., SKILL, Perl).
• Interface with board fabrication vendors to apply impedance rules, DFM and DFT rule sets.
• Collaborate with hardware engineers, PCB designers and fabricators to develop and maintain products.
• Stay updated on PCB industry standards and technologies.

Skills

High-speed board design

Technical leadership

Schematic entry understanding

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, or related field, or equivalent practical experience

Master’s or PhD in Electrical Engineering, Computer Engineering, Physics, or related field

Tools

OrCAD

Concept

Allegro

Job description

Share Senior PCB Layout Engineer, Google Cloud

corporate_fare Google place Sunnyvale, CA, USA

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
• 4 years of experience working in PCB design, or 3 years of experience with an advanced degree.
• Experience working with CAD tools such as OrCAD, Concept, and Allegro.
• Experience working with PCB design tools and methodology.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field.
• 1 year of experience in technical leadership.
• Experience with mechanical design.
• Experience with all phases of hardware development, including schematic entry, manually generated constraints or understanding the requirements of the constraints, and board layout.
• Experience with high-speed board design/layout.

About the job

As a Senior PCB Layout Engineer designer on the Platforms Infrastructure team, you will be working on developing fast-paced board programs. You will work with hardware, mechanical, and manufacturing engineers throughout the full product development life-cycle, supporting PCB placement and routing design.

In this role, you will work as an integral part of the Systems Hardware Development team, interfacing with external fabricators/vendors to apply industry standards, CAD/layout tools and technologies.

Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by cutting-edge custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concept all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers, affecting millions of Google users.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google .

• Create PCB outline and layer setup, component placement and signal routing.
• Write and maintain scripts related to PCB design, Design for Manufacturing (DFM), and release (e.g., SKILL, Perl, etc.).
• Interface with board fabrication vendors to select and use correct impedance rules, DFM and Design for Test (DFT)rule sets.
• Work with hardware engineers, PCB designers and fabricators to develop and maintain actual products.
• Be updated on PCB industry standards and technologies.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.