Senior Micro-Architect: Coherent Interconnect RTL

Lehigh Heavy Forge Corporation; San Jose (CA); On-site; USD 151,000 - 252,000; Full time

Benefits offered by this job

Medical

Dental

Vision

401(k)

Relocation assistance

Job summary

Samsung Electronics America, Inc. seeks a Micro-Architect/Logic Designer to lead RTL design for coherent interconnect IP and LLC blocks. You will partner with architects to shape next-gen interconnects and drive timing, area, and power optimizations across the design flow.

You will collaborate with verification, performance/power, and CAD teams, mentor junior engineers, and ensure on-schedule RTL quality meeting PPA goals in a global, dynamic environment.

Qualifications

• Bachelor’s degree in Computer Science, Computer Engineering or related technical field.
• 4+ years with Master’s degree or 2+ years with PhD considered for senior levels.
• Proven RTL design experience for coherent interconnect or LLC in high perf. digital designs.
• Strong Verilog and ASIC flow knowledge: RTL design, verification, synthesis, DFT, timing, floorplanning.

Responsibilities

• Lead micro-architecture development of coherent interconnect IP and LLC blocks.
• Collaborate with architects to define next-gen interconnects.
• Drive RTL design, timing and area optimizations.
• Verify functionality with the verification team and support lab debug.
• Mentor junior engineers and guide design reviews.

Skills

RTL design ownership

Verilog

AMBA CHI/AXI/ACE

System caches/protocols

Team leadership

Timing/power optimization

DFT/EC/Timing analysis

Education

Bachelor’s in CS/CE or related field

Master’s preferred or PhD/4+ yrs experience

Job description

Samsung Electronics America, Inc. seeks a Micro-Architect/Logic Designer to lead RTL design for coherent interconnect IP and LLC blocks. You will partner with architects to shape next-gen interconnects and drive timing, area, and power optimizations across the design flow.

You will collaborate with verification, performance/power, and CAD teams, mentor junior engineers, and ensure on-schedule RTL quality meeting PPA goals in a global, dynamic environment.