Senior IC Verification Architect - SystemVerilog/UVM

Insight Global; San Jose (CA); On-site; USD 140,000 - 220,000; Full time

Job summary

Insight Global is seeking senior IC Verification Engineers with deep hands-on SystemVerilog and UVM expertise. You will own the verification lifecycle, including testbench architecture, test planning, functional coverage, regression debugging, hardware debug, and verification closure.

Architect scalable and reusable SystemVerilog/UVM testbenches and develop verification strategies for block, core, and SoC features.

Qualifications

• 10+ years of ASIC/SoC verification experience.
• Experience with full ASIC cycle from architecture to tapeout.
• Expert in SystemVerilog and UVM.

Responsibilities

• Architect scalable and reusable SystemVerilog/UVM testbenches
• Develop verification strategies and test plans for block, core, and SoC features
• Build constrained-random and pseudo-random tests
• Develop functional coverage and drive verification to closure
• Debug regression failures and address coverage gaps
• Support hardware debug and full ASIC-cycle execution
• Document verification environments, tests, and strategies
• Collaborate with design and architecture teams

Skills

SystemVerilog

UVM

Verification planning

Constrained-random testing

Testbench architecture

Regression debugging

Hardware debug

Waveform analysis

Coverage closure

Lead verification

Tools

SystemVerilog

UVM

Job description

Insight Global is seeking senior IC Verification Engineers with deep hands-on SystemVerilog and UVM expertise. You will own the verification lifecycle, including testbench architecture, test planning, functional coverage, regression debugging, hardware debug, and verification closure.

Architect scalable and reusable SystemVerilog/UVM testbenches and develop verification strategies for block, core, and SoC features.